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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [CI v5 15/18] drm/i915/display: Helpers for VRR vblank min and max start
Date: Mon, 25 Jan 2021 13:42:08 +0200	[thread overview]
Message-ID: <YA6ukB0Pq8HzczJw@intel.com> (raw)
In-Reply-To: <20210122232647.22688-15-manasi.d.navare@intel.com>

On Fri, Jan 22, 2021 at 03:26:44PM -0800, Manasi Navare wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> With VRR the earliest the registers can get latched are at
> flipline decision boundary, calculate that as vrr_vmin_vblank_start()
> and the latest the regsiters can get latched are vmax decision boundary
> calculate that as vrr_vmax_vblank_start()
> 
> v2:
> * Remove TODO and adjust extra scanline const (Manasi)
> 
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 36 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
>  2 files changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index c71254563a10..49ff5add90e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -45,6 +45,42 @@ intel_vrr_check_modeset(struct intel_atomic_state *state)
>  	}
>  }
>  
> +/*
> + * Without VRR registers get latched at:
> + *  vblank_start
> + *
> + * With VRR the earliest registers can get latched is:
> + *  intel_vrr_vmin_vblank_start(), which if we want to maintain
> + *  the correct min vtotal is >=vblank_start+1
> + *
> + * The latest point registers can get latched is the vmax decision boundary:
> + *  intel_vrr_vmax_vblank_start()
> + *
> + * Between those two points the vblank exit starts (and hence registers get
> + * latched) ASAP after a push is sent.
> + *
> + * framestart_delay is programmable 0-3.

"1-4" now

> + */
> +static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> +	/* The hw imposes the extra scanline before frame start */
> +	return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
> +}
> +
> +int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> +{
> +	/* Min vblank actually determined by flipline that is always >=vmin+1 */
> +	return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
> +}
> +
> +int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
> +{
> +	return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
> +}
> +
>  void
>  intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  			 struct drm_connector_state *conn_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 7610051edad2..d8b6b45557ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -27,5 +27,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
>  void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
>  void intel_vrr_get_config(struct intel_crtc *crtc,
>  			  struct intel_crtc_state *crtc_state);
> +int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_VRR_H__ */
> -- 
> 2.19.1

-- 
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2021-01-25 11:42 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-22 23:26 [Intel-gfx] [CI v5 01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 02/18] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 03/18] drm/i915: Store framestart_delay in dev_priv Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 04/18] drm/i915: Extract intel_mode_vblank_start() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp() Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 06/18] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2021-01-25 11:41   ` Ville Syrjälä
2021-01-22 23:26 ` [Intel-gfx] [CI v5 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 08/18] drm/i915/display: VRR + DRRS cannot be enabled together Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 09/18] drm/i915: Rename VRR_CTL reg fields Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 11/18] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 14/18] drm/i915/display: Add HW state readout for VRR Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 15/18] drm/i915/display: Helpers for VRR vblank min and max start Manasi Navare
2021-01-25 11:42   ` Ville Syrjälä [this message]
2021-01-22 23:26 ` [Intel-gfx] [CI v5 16/18] drm/i915: Add vrr state dump Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 17/18] drm/i915: Fix vblank timestamps with VRR Manasi Navare
2021-01-22 23:26 ` [Intel-gfx] [CI v5 18/18] drm/i915: Fix vblank evasion with vrr Manasi Navare
2021-01-23  2:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v5,01/18] drm/i915/display/vrr: Create VRR file and add VRR capability check Patchwork
2021-01-23  2:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-23  3:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-23 13:56 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-01-25 20:08 ` [Intel-gfx] [CI v6] " Manasi Navare
2021-01-25 20:36 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,v6] drm/i915/display/vrr: Create VRR file and add VRR capability check (rev2) Patchwork
2021-01-25 20:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-25 21:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-01-26  2:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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