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dmarc=none action=none header.from=oracle.com; Date: Mon, 25 Jan 2021 13:42:16 -0500 From: Boris Ostrovsky To: Jan Beulich Cc: iwj@xenproject.org, wl@xen.org, anthony.perard@citrix.com, andrew.cooper3@citrix.com, roger.pau@citrix.com, jun.nakajima@intel.com, kevin.tian@intel.com, xen-devel@lists.xenproject.org Subject: Re: [PATCH v2 3/4] x86: Allow non-faulting accesses to non-emulated MSRs if policy permits this Message-ID: References: <1611182952-9941-1-git-send-email-boris.ostrovsky@oracle.com> <1611182952-9941-4-git-send-email-boris.ostrovsky@oracle.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Originating-IP: [138.3.200.58] X-ClientProxiedBy: BYAPR04CA0030.namprd04.prod.outlook.com (2603:10b6:a03:40::43) To BYAPR10MB3288.namprd10.prod.outlook.com (2603:10b6:a03:156::21) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 173f594d-2911-439e-748c-08d8c160f360 X-MS-TrafficTypeDiagnostic: BY5PR10MB4227: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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X-MS-Exchange-AntiSpam-MessageData: 8TPFZj3pnjTAifNCfckmTdHomIw+HTT6jAQDrUFKIZzVHgaWPOZAhIGoa2P5vKPztTqlY27hEd1L6oAb8B7D3S5WpqxefSNI5n1u+9vtxk61VrcRy4P/EbtOO0fGjT5x3tLZN0fnP6tTdqeoq/N4zkl03hDVPzY2GqvnLWNED8TzVMxECA0lQMqEgWM2kf329ZhzSudOEksFs3pjFYsH794KloiZPfRjjbM0ydlF2Mj6GoPjUgcCxxLBzQc4158r5VDNqgkPiYt2I7gwErATgehMxJIpjec9ra2wh3Hqq9Gbo4lWozUc/1Pz19klX3a4Sg+W6tHlCGOixVPljOw0NFLvzq9/TG7NeCEY515fArkPuk1q0Ct5g9XHQtM7nRTuVbPgtVCSY9KgvO5yYzIKd/nU8qx+T2qHzAadaE6KE7MwolpLm1dZ3qcWyYbR3cUrse5ztM6ApmYd187EKyF2h3QsAdId4lyYqZnj0qZiJxwgGW/agLey83vNfaHiqtj1aWP+0ED3KlenJrG/aCKkFNQTq6i6Q2cH7feF/Hd59R4ROb1/0oP0Se6lE34fUNcruONLPycQTva7eDUHhGE4Up8R2ACA2EF535CSfxZ7d1dpy/b/lLp9uBvckyg7al5BU+eRCW1UqVkXxrK9P2fnTS6kNWfA4owgDvdyebc7ziQwJfc0SbDxSpCiuwKhvjhIxDkRmPacCiSpE3B568gL+sjfA2D9t3/FNZ77SozczTlA7kLSXIWEBSHdS874Kqrf X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-Network-Message-Id: 173f594d-2911-439e-748c-08d8c160f360 X-MS-Exchange-CrossTenant-AuthSource: BYAPR10MB3288.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2021 18:42:22.4327 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wXCzO/fX/OZ+t/+iAx3OdgrVVxhlYnwjOjqpXg0ulpF7ZWbgaI1ZZ6NDH114Wlkl2ZSZf7VZNyVLuNAWxFprzBI9wHmgXh/tQiBClwowGNc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR10MB4227 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=9875 signatures=668683 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 spamscore=0 phishscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2101250099 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=9875 signatures=668683 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2101250099 On 21-01-25 11:22:08, Jan Beulich wrote: > On 22.01.2021 20:52, Boris Ostrovsky wrote: > > On 1/22/21 7:51 AM, Jan Beulich wrote: > >> On 20.01.2021 23:49, Boris Ostrovsky wrote: > >>> + > >>> + /* > >>> + * Accesses to unimplemented MSRs as part of emulation of instructions > >>> + * other than guest's RDMSR/WRMSR should never succeed. > >>> + */ > >>> + if ( !is_guest_msr_access ) > >>> + ignore_msrs = MSR_UNHANDLED_NEVER; > >> > >> Wouldn't you better "return true" here? Such accesses also > >> shouldn't be logged imo (albeit I agree that's a change from > >> current behavior). > > > > > > Yes, that's why I didn't return here. We will be here in !is_guest_msr_access case most likely due to a bug in the emulator so I think we do want to see the error logged. > > Why "most likely"? OK, definitely ;-) But I still think logging these accesses would be helpful. > > >>> + if ( unlikely(ignore_msrs != MSR_UNHANDLED_NEVER) ) > >>> + *val = 0; > >> > >> I don't understand the conditional here, even more so with > >> the respective changelog entry. In any event you don't > >> want to clobber the value ahead of ... > >> > >>> + if ( likely(ignore_msrs != MSR_UNHANDLED_SILENT) ) > >>> + { > >>> + if ( is_write ) > >>> + gdprintk(XENLOG_WARNING, "WRMSR 0x%08x val 0x%016"PRIx64 > >>> + " unimplemented\n", msr, *val); > >> > >> ... logging it. > > > > > > True. I dropped !is_write from v1 without considering this. > > > > As far as the conditional --- dropping it too would be a behavior change. > > Albeit an intentional one then? Plus I think I have trouble > seeing what behavior it would be that would change. Currently callers of, say, read_msr() don't expect the argument that they pass in to change. Granted, they shouldn't (and AFAICS don't) look at it but it's a change nonetheless. > > >>> --- a/xen/arch/x86/x86_emulate/x86_emulate.h > >>> +++ b/xen/arch/x86/x86_emulate/x86_emulate.h > >>> @@ -850,4 +850,10 @@ static inline void x86_emul_reset_event(struct x86_emulate_ctxt *ctxt) > >>> ctxt->event = (struct x86_event){}; > >>> } > >>> > >>> +static inline bool x86_emul_guest_msr_access(struct x86_emulate_ctxt *ctxt) > >> > >> The parameter wants to be pointer-to-const. In addition I wonder > >> whether this wouldn't better be a sibling to > >> x86_insn_is_cr_access() (without a "state" parameter, which > >> would be unused and unavailable to the callers), which may end > >> up finding further uses down the road. > > > > > > "Sibling" in terms of name (yes, it would be) or something else? > > Name and (possible) purpose - a validate hook could want to > make use of this, for example. A validate hook? > > >>> +{ > >>> + return ctxt->opcode == X86EMUL_OPC(0x0f, 0x32) || /* RDMSR */ > >>> + ctxt->opcode == X86EMUL_OPC(0x0f, 0x30); /* WRMSR */ > >>> +} > >> > >> Personally I'd prefer if this was a single comparison: > >> > >> return (ctxt->opcode | 2) == X86EMUL_OPC(0x0f, 0x32); > >> > >> But maybe nowadays' compilers are capable of this > >> transformation? > > > > Here is what I've got (not an inline but shouldn't make much difference I'd think) > > > > ffff82d040385960 : # your code > > ffff82d040385960: 8b 47 2c mov 0x2c(%rdi),%eax > > ffff82d040385963: 83 e0 fd and $0xfffffffd,%eax > > ffff82d040385966: 3d 30 00 0f 00 cmp $0xf0030,%eax > > ffff82d04038596b: 0f 94 c0 sete %al > > ffff82d04038596e: c3 retq > > > > ffff82d04038596f : # my code > > ffff82d04038596f: 8b 47 2c mov 0x2c(%rdi),%eax > > ffff82d040385972: 83 c8 02 or $0x2,%eax > > ffff82d040385975: 3d 32 00 0f 00 cmp $0xf0032,%eax > > ffff82d04038597a: 0f 94 c0 sete %al > > ffff82d04038597d: c3 retq > > > > > > So it's a wash in terms of generated code. > > True, albeit I guess you got "your code" and "my code" the > wrong way round, as I don't expect the compiler to > translate | into "and". Yes, looks like I did switch them. > > >> I notice you use this function only from PV priv-op emulation. > >> What about the call paths through hvmemul_{read,write}_msr()? > >> (It's also questionable whether the write paths need this - > >> the only MSR written outside of WRMSR emulation is > >> MSR_SHADOW_GS_BASE, which can't possibly reach the "unhandled" > >> logic anywhere. But maybe better to be future proof here in > >> case new MSR writes appear in the emulator, down the road.) > > > > > > Won't we end up in hvm_funcs.msr_write_intercept ops which do call it? > > Of course we will - the boolean will very likely need > propagating (a possible alternative being a per-vCPU flag > indicating "in emulator"). Oh, I see what you mean. By per-vcpu flag you mean arch_vcpu field I assume? -boris