[PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme

[PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme

[AngeloGioacchino Del Regno]

The TCSR's PHY_CLK_SCHEME register is not available on all SoC
models, but some may still use a differential reference clock.

In preparation for these SoCs, add a se_clk_scheme_default
configuration entry and declare it to true for all currently
supported SoCs (retaining the previous defaults.

This patch brings no functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 drivers/phy/qualcomm/phy-qcom-qusb2.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 109792203baf..8fcfea2a8f1f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -245,6 +245,9 @@ struct qusb2_phy_cfg {
 
 	/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
 	bool has_pll_override;
+
+	/* true if PHY default clk scheme is single-ended */
+	bool se_clk_scheme_default;
 };
 
 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
@@ -253,6 +256,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
 	.regs		= msm8996_regs_layout,
 
 	.has_pll_test	= true,
+	.se_clk_scheme_default = true,
 	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 	.mask_core_ready = PLL_LOCKED,
 	.autoresume_en	 = BIT(3),
@@ -266,6 +270,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
 	.disable_ctrl   = POWER_DOWN,
 	.mask_core_ready = CORE_READY_STATUS,
 	.has_pll_override = true,
+	.se_clk_scheme_default = true,
 	.autoresume_en   = BIT(0),
 	.update_tune1_with_efuse = true,
 };
@@ -279,6 +284,7 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
 			   POWER_DOWN),
 	.mask_core_ready = CORE_READY_STATUS,
 	.has_pll_override = true,
+	.se_clk_scheme_default = true,
 	.autoresume_en	  = BIT(0),
 	.update_tune1_with_efuse = true,
 };
@@ -701,8 +707,13 @@ static int qusb2_phy_init(struct phy *phy)
 	/* Required to get phy pll lock successfully */
 	usleep_range(150, 160);
 
-	/* Default is single-ended clock on msm8996 */
-	qphy->has_se_clk_scheme = true;
+	/*
+	 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
+	 * register in the TCSR so, if there's none, use the default
+	 * value hardcoded in the configuration.
+	 */
+	qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
+
 	/*
 	 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
 	 * clock scheme is selected. If yes, then disable differential
-- 
2.29.2

[PATCH 2/3] phy: qcom-qusb2: Add configuration for SDM660

[AngeloGioacchino Del Regno]

The SDM660 SoC uses the same configuration as MSM8996, but the
clock scheme uses a differential reference clock and none of
the SoCs in this series (630, 636 and others) have got a usable
PHY_CLK_SCHEME register in the TCSR for clk scheme detection.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 drivers/phy/qualcomm/phy-qcom-qusb2.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 8fcfea2a8f1f..3629f60460a1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -289,6 +289,19 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
 	.update_tune1_with_efuse = true,
 };
 
+static const struct qusb2_phy_cfg sdm660_phy_cfg = {
+	.tbl		= msm8996_init_tbl,
+	.tbl_num	= ARRAY_SIZE(msm8996_init_tbl),
+	.regs		= msm8996_regs_layout,
+
+	.has_pll_test	= true,
+	.se_clk_scheme_default = false,
+	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
+	.mask_core_ready = PLL_LOCKED,
+	.autoresume_en	 = BIT(3),
+};
+
+
 static const char * const qusb2_phy_vreg_names[] = {
 	"vdda-pll", "vdda-phy-dpdm",
 };
@@ -829,6 +842,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
 	}, {
 		.compatible	= "qcom,msm8998-qusb2-phy",
 		.data		= &msm8998_phy_cfg,
+	}, {
+		.compatible	= "qcom,sdm660-qusb2-phy",
+		.data		= &sdm660_phy_cfg,
 	}, {
 		/*
 		 * Deprecated. Only here to support legacy device
-- 
2.29.2

[PATCH 3/3] dt-bindings: phy: qcom-qusb2: Document SDM660 compatible

[AngeloGioacchino Del Regno]

Support for the SDM630/660 series of SoCs was added to the driver:
document the qcom,sdm660-qusb2-phy compatible here.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
index d457fb6a4779..582abbbd8b32 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -21,6 +21,7 @@ properties:
               - qcom,ipq8074-qusb2-phy
               - qcom,msm8996-qusb2-phy
               - qcom,msm8998-qusb2-phy
+              - qcom,sdm660-qusb2-phy
       - items:
           - enum:
               - qcom,sc7180-qusb2-phy
-- 
2.29.2

Re: [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme

[Bjorn Andersson]

On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:

> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
> models, but some may still use a differential reference clock.
> 
> In preparation for these SoCs, add a se_clk_scheme_default
> configuration entry and declare it to true for all currently
> supported SoCs (retaining the previous defaults.
> 
> This patch brings no functional changes.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qusb2.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index 109792203baf..8fcfea2a8f1f 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -245,6 +245,9 @@ struct qusb2_phy_cfg {
>  
>  	/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
>  	bool has_pll_override;
> +
> +	/* true if PHY default clk scheme is single-ended */
> +	bool se_clk_scheme_default;
>  };
>  
>  static const struct qusb2_phy_cfg msm8996_phy_cfg = {
> @@ -253,6 +256,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
>  	.regs		= msm8996_regs_layout,
>  
>  	.has_pll_test	= true,
> +	.se_clk_scheme_default = true,
>  	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
>  	.mask_core_ready = PLL_LOCKED,
>  	.autoresume_en	 = BIT(3),
> @@ -266,6 +270,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
>  	.disable_ctrl   = POWER_DOWN,
>  	.mask_core_ready = CORE_READY_STATUS,
>  	.has_pll_override = true,
> +	.se_clk_scheme_default = true,
>  	.autoresume_en   = BIT(0),
>  	.update_tune1_with_efuse = true,
>  };
> @@ -279,6 +284,7 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
>  			   POWER_DOWN),
>  	.mask_core_ready = CORE_READY_STATUS,
>  	.has_pll_override = true,
> +	.se_clk_scheme_default = true,
>  	.autoresume_en	  = BIT(0),
>  	.update_tune1_with_efuse = true,
>  };
> @@ -701,8 +707,13 @@ static int qusb2_phy_init(struct phy *phy)
>  	/* Required to get phy pll lock successfully */
>  	usleep_range(150, 160);
>  
> -	/* Default is single-ended clock on msm8996 */
> -	qphy->has_se_clk_scheme = true;
> +	/*
> +	 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
> +	 * register in the TCSR so, if there's none, use the default
> +	 * value hardcoded in the configuration.
> +	 */
> +	qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
> +
>  	/*
>  	 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
>  	 * clock scheme is selected. If yes, then disable differential
> -- 
> 2.29.2
> 

Re: [PATCH 2/3] phy: qcom-qusb2: Add configuration for SDM660

[Bjorn Andersson]

On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:

> The SDM660 SoC uses the same configuration as MSM8996, but the
> clock scheme uses a differential reference clock and none of
> the SoCs in this series (630, 636 and others) have got a usable
> PHY_CLK_SCHEME register in the TCSR for clk scheme detection.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qusb2.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index 8fcfea2a8f1f..3629f60460a1 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -289,6 +289,19 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
>  	.update_tune1_with_efuse = true,
>  };
>  
> +static const struct qusb2_phy_cfg sdm660_phy_cfg = {
> +	.tbl		= msm8996_init_tbl,
> +	.tbl_num	= ARRAY_SIZE(msm8996_init_tbl),
> +	.regs		= msm8996_regs_layout,
> +
> +	.has_pll_test	= true,
> +	.se_clk_scheme_default = false,
> +	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> +	.mask_core_ready = PLL_LOCKED,
> +	.autoresume_en	 = BIT(3),
> +};
> +
> +
>  static const char * const qusb2_phy_vreg_names[] = {
>  	"vdda-pll", "vdda-phy-dpdm",
>  };
> @@ -829,6 +842,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
>  	}, {
>  		.compatible	= "qcom,msm8998-qusb2-phy",
>  		.data		= &msm8998_phy_cfg,
> +	}, {
> +		.compatible	= "qcom,sdm660-qusb2-phy",
> +		.data		= &sdm660_phy_cfg,
>  	}, {
>  		/*
>  		 * Deprecated. Only here to support legacy device
> -- 
> 2.29.2
> 

Re: [PATCH 3/3] dt-bindings: phy: qcom-qusb2: Document SDM660 compatible

[Bjorn Andersson]

On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:

> Support for the SDM630/660 series of SoCs was added to the driver:
> document the qcom,sdm660-qusb2-phy compatible here.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> ---
>  Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> index d457fb6a4779..582abbbd8b32 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> @@ -21,6 +21,7 @@ properties:
>                - qcom,ipq8074-qusb2-phy
>                - qcom,msm8996-qusb2-phy
>                - qcom,msm8998-qusb2-phy
> +              - qcom,sdm660-qusb2-phy
>        - items:
>            - enum:
>                - qcom,sc7180-qusb2-phy
> -- 
> 2.29.2
> 

Re: [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme

[AngeloGioacchino Del Regno]

Il 14/01/21 18:52, Bjorn Andersson ha scritto:
> On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:
> 
>> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
>> models, but some may still use a differential reference clock.
>>
>> In preparation for these SoCs, add a se_clk_scheme_default
>> configuration entry and declare it to true for all currently
>> supported SoCs (retaining the previous defaults.
>>
>> This patch brings no functional changes.
>>
> 
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> 

Thanks!! :)

>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qusb2.c | 15 +++++++++++++--
>>   1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> index 109792203baf..8fcfea2a8f1f 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> @@ -245,6 +245,9 @@ struct qusb2_phy_cfg {
>>   
>>   	/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
>>   	bool has_pll_override;
>> +
>> +	/* true if PHY default clk scheme is single-ended */
>> +	bool se_clk_scheme_default;
>>   };
>>   
>>   static const struct qusb2_phy_cfg msm8996_phy_cfg = {
>> @@ -253,6 +256,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
>>   	.regs		= msm8996_regs_layout,
>>   
>>   	.has_pll_test	= true,
>> +	.se_clk_scheme_default = true,
>>   	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
>>   	.mask_core_ready = PLL_LOCKED,
>>   	.autoresume_en	 = BIT(3),
>> @@ -266,6 +270,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
>>   	.disable_ctrl   = POWER_DOWN,
>>   	.mask_core_ready = CORE_READY_STATUS,
>>   	.has_pll_override = true,
>> +	.se_clk_scheme_default = true,
>>   	.autoresume_en   = BIT(0),
>>   	.update_tune1_with_efuse = true,
>>   };
>> @@ -279,6 +284,7 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
>>   			   POWER_DOWN),
>>   	.mask_core_ready = CORE_READY_STATUS,
>>   	.has_pll_override = true,
>> +	.se_clk_scheme_default = true,
>>   	.autoresume_en	  = BIT(0),
>>   	.update_tune1_with_efuse = true,
>>   };
>> @@ -701,8 +707,13 @@ static int qusb2_phy_init(struct phy *phy)
>>   	/* Required to get phy pll lock successfully */
>>   	usleep_range(150, 160);
>>   
>> -	/* Default is single-ended clock on msm8996 */
>> -	qphy->has_se_clk_scheme = true;
>> +	/*
>> +	 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
>> +	 * register in the TCSR so, if there's none, use the default
>> +	 * value hardcoded in the configuration.
>> +	 */
>> +	qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
>> +
>>   	/*
>>   	 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
>>   	 * clock scheme is selected. If yes, then disable differential
>> -- 
>> 2.29.2
>>

Re: [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme

[Vinod Koul]

On 14-01-21, 18:47, AngeloGioacchino Del Regno wrote:
> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
> models, but some may still use a differential reference clock.
> 
> In preparation for these SoCs, add a se_clk_scheme_default
> configuration entry and declare it to true for all currently
> supported SoCs (retaining the previous defaults.
> 
> This patch brings no functional changes.

Patch 2 had two blank lines getting inserted, I have fixed that up while
applying.. so:

Applied all, thanks

-- 
~Vinod

Re: [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme

[AngeloGioacchino Del Regno]

Il 19/01/21 16:07, Vinod Koul ha scritto:
> Patch 2 had two blank lines getting inserted, I have fixed that up while
> applying.. so:
> 
> Applied all, thanks

Thank you!