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From: Sean Christopherson <seanjc@google.com>
To: Dave Hansen <dave.hansen@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Joerg Roedel <jroedel@suse.de>,
	David Rientjes <rientjes@google.com>,
	Borislav Petkov <bp@alien8.de>, Andy Lutomirski <luto@kernel.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Brijesh Singh <brijesh.singh@amd.com>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Jon Grimm <jon.grimm@amd.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Christoph Hellwig <hch@lst.de>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Ingo Molnar <mingo@redhat.com>,
	x86@kernel.org, linux-mm@kvack.org
Subject: Re: AMD SEV-SNP/Intel TDX: validation of memory pages
Date: Fri, 12 Feb 2021 10:22:01 -0800	[thread overview]
Message-ID: <YCbHSW1VPQqaU1M4@google.com> (raw)
In-Reply-To: <e07e5abd-72c3-17fb-6c65-19bdfc76382e@intel.com>

On Fri, Feb 12, 2021, Dave Hansen wrote:
> On 2/12/21 8:45 AM, Peter Zijlstra wrote:
> > But you're right, if a HV injects #VE in the syscall gap and gets a
> > concurrent CPU to 'fix' the exception frame (which then lives on the
> > user stack) the handler might never know it went ga-ga.
> > 
> > Is this something the TDX thread model covers? A malicous HV and a TDX
> > guest co-operating to bring down the guest kernel.
> 
> I'll say this: The current TDX guest code that Sathya posted is
> predicated on an assumption that an malicious HV can not inject a #VE in
> the syscall gap, or any of the other sensitive paths.
> 
> A #VE in the syscall gap is just as fatal as a #PF or #GP would be
> there.  If TDX can't provide guarantees to the guest that a #VE won't
> happen there, then TDX is broken, or the kernel implementation is broken.
> 
> If anyone knows of any way for a HV to inject #VE in the syscall gap,
> please speak up.  Better to know now.

Removing and reinserting the SYSCALL page (or any other page touched in the
SYSCALL gap) will result in a #VE, as TDX behavior is to generate a #VE on an
access to an unaccepated.

Andy L pointed out this conundrum a while back.  My hack idea to "solve" this
was to add an API to the TDX-Module that would allow the guest kernel to define
a set of GPAs that must never #VE.

https://lkml.kernel.org/r/20200825171903.GA20660@sjchrist-ice


  reply	other threads:[~2021-02-12 18:22 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-02  1:51 AMD SEV-SNP/Intel TDX: validation of memory pages David Rientjes
2021-02-02 13:17 ` Matthew Wilcox
2021-02-02 16:02 ` Kirill A. Shutemov
2021-02-03  0:16   ` Brijesh Singh
2021-02-11 17:46     ` Sean Christopherson
2021-02-02 22:37 ` Andi Kleen
2021-02-11 20:46 ` Peter Zijlstra
2021-02-12 13:19 ` Joerg Roedel
2021-02-12 14:17   ` Peter Zijlstra
2021-02-12 14:53     ` Joerg Roedel
2021-02-12 15:19       ` Peter Zijlstra
2021-02-12 15:28         ` Joerg Roedel
2021-02-12 16:12           ` Peter Zijlstra
2021-02-12 16:18             ` Joerg Roedel
2021-02-12 16:45               ` Peter Zijlstra
2021-02-12 17:48                 ` Dave Hansen
2021-02-12 18:22                   ` Sean Christopherson [this message]
2021-02-12 18:38                     ` Andy Lutomirski
2021-02-12 18:43                       ` Sean Christopherson
2021-02-12 18:46                     ` Dave Hansen
2021-02-12 19:24                       ` Sean Christopherson
2021-02-16 10:00                 ` Joerg Roedel
2021-02-16 14:27                   ` Andi Kleen
2021-02-16 14:46                     ` Peter Zijlstra
2021-02-16 15:59                       ` Paolo Bonzini
2021-02-16 16:25                         ` Joerg Roedel
2021-02-16 16:48                           ` Paolo Bonzini
2021-02-16 18:26                             ` Joerg Roedel
2021-02-16 18:33                               ` Paolo Bonzini
2021-02-16 16:47                         ` Peter Zijlstra
2021-02-16 16:57                         ` Andy Lutomirski
2021-02-16 17:05                           ` Paolo Bonzini
2021-02-16 16:55                       ` Andi Kleen
2021-02-12 21:42             ` Andi Kleen
2021-02-12 21:58               ` Peter Zijlstra
2021-02-12 22:39                 ` Andi Kleen
2021-02-12 22:46                   ` Andy Lutomirski
2021-02-13  9:38                   ` Peter Zijlstra
2021-02-12 23:51                 ` Paolo Bonzini
2021-03-23  9:33 ` Joerg Roedel

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