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From: Peter Zijlstra <peterz@infradead.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>, Joerg Roedel <jroedel@suse.de>,
	David Rientjes <rientjes@google.com>,
	Borislav Petkov <bp@alien8.de>, Andy Lutomirski <luto@kernel.org>,
	Sean Christopherson <seanjc@google.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
	Brijesh Singh <brijesh.singh@amd.com>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Jon Grimm <jon.grimm@amd.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Christoph Hellwig <hch@lst.de>, Ingo Molnar <mingo@redhat.com>,
	x86@kernel.org, linux-mm@kvack.org
Subject: Re: AMD SEV-SNP/Intel TDX: validation of memory pages
Date: Tue, 16 Feb 2021 17:47:30 +0100	[thread overview]
Message-ID: <YCv3Img2HBJX5GU/@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <5ff9690f-331a-8322-3431-212b14f64fcc@redhat.com>

On Tue, Feb 16, 2021 at 04:59:52PM +0100, Paolo Bonzini wrote:
> On 16/02/21 15:46, Peter Zijlstra wrote:
> > On Tue, Feb 16, 2021 at 06:27:41AM -0800, Andi Kleen wrote:
> > > I think the IST solution should at least be explored before
> > > dismissing it. It might be simpler than anything else (like
> > > using new APIs)
> > 
> > Have you seen the trainwreck bonzini proposed?
> 
> You had been suspiciously silent...

:-)

> > The very simplest thing is saying no to TDX.
> > 
> > That 'solution' also hard relies on #VE not nesting more than once, so
> > lovely things like: #VE -> #DB -> #VE -> #NMI -> #VE, or #VE -> NMI ->
> > #VE -> #MC -> #VE or any number of other possible 'fun' combinations
> > _must_ not happen.
> 
> ... but no, this is not how it works.  It is actually guaranteed that #VE
> does not nest more than once, and that's the big difference with NMIs.

Note that our NMI entry code is broken vs #MC or any other exception
that can land while we're setting up that recursion mess.

> Let's look at the first case you listed, this is what would happen:
> 
> 
> #VE handler starts on stack 1
> First #VE processing...
> clear VE-in-progress flag in the info block (allowing reentrancy)
> 	#DB handler starts
> 		nested #VE handler starts on stack 2

NMI can't land here because of the special ductape? The inner #VE never
clears VE-in-progress.

> 		outer #VE handler marks stack 1 for reexecution
> 		nested #VE handler ends ***
> 	#DB handler ends

So what does the #DB memop that triggered that #VE actually read? What
if it was a store?

Because clearly it will not have handled the on-demand validation thing.
So how can memops proceed?

> #VE handler IRETs back to the start of the handler itself
> Second #VE processing starts (also on stack 1)
> clear VE-in-progress flag in the info block
> 	#NMI handler
> 		nested #VE handler starts on stack 2
> 		outer #VE handler marks stack 1 for reexecution
> 		nested #VE handler ends ***
> 	#NMI handler ends
> #VE handler IRETs back to the start of the handler itself
> Third #VE processing starts (also on stack 1)
> clear VE-in-progress flag in the info block
> #VE handler IRETs back to the caller
> 
> 
> Two things of note:
> 
> - note that at the points marked *** the nested #VE handler has not allowed
> another exception to come.  That only happens in the outer handler.
> 
> - the inner handler does nothing but telling the outer handler to rerun.
> The way it does it is certainly not pretty, because it has to work at any
> instruction boundary, but at its heart it's basically a do{}while loop.

So this hard relies on inhibiting NMIs and #MC being busted, right? But
I still don't understand what happens to the memops if you don't handle
the #VE.


  parent reply	other threads:[~2021-02-16 16:49 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-02  1:51 AMD SEV-SNP/Intel TDX: validation of memory pages David Rientjes
2021-02-02 13:17 ` Matthew Wilcox
2021-02-02 16:02 ` Kirill A. Shutemov
2021-02-03  0:16   ` Brijesh Singh
2021-02-11 17:46     ` Sean Christopherson
2021-02-02 22:37 ` Andi Kleen
2021-02-11 20:46 ` Peter Zijlstra
2021-02-12 13:19 ` Joerg Roedel
2021-02-12 14:17   ` Peter Zijlstra
2021-02-12 14:53     ` Joerg Roedel
2021-02-12 15:19       ` Peter Zijlstra
2021-02-12 15:28         ` Joerg Roedel
2021-02-12 16:12           ` Peter Zijlstra
2021-02-12 16:18             ` Joerg Roedel
2021-02-12 16:45               ` Peter Zijlstra
2021-02-12 17:48                 ` Dave Hansen
2021-02-12 18:22                   ` Sean Christopherson
2021-02-12 18:38                     ` Andy Lutomirski
2021-02-12 18:43                       ` Sean Christopherson
2021-02-12 18:46                     ` Dave Hansen
2021-02-12 19:24                       ` Sean Christopherson
2021-02-16 10:00                 ` Joerg Roedel
2021-02-16 14:27                   ` Andi Kleen
2021-02-16 14:46                     ` Peter Zijlstra
2021-02-16 15:59                       ` Paolo Bonzini
2021-02-16 16:25                         ` Joerg Roedel
2021-02-16 16:48                           ` Paolo Bonzini
2021-02-16 18:26                             ` Joerg Roedel
2021-02-16 18:33                               ` Paolo Bonzini
2021-02-16 16:47                         ` Peter Zijlstra [this message]
2021-02-16 16:57                         ` Andy Lutomirski
2021-02-16 17:05                           ` Paolo Bonzini
2021-02-16 16:55                       ` Andi Kleen
2021-02-12 21:42             ` Andi Kleen
2021-02-12 21:58               ` Peter Zijlstra
2021-02-12 22:39                 ` Andi Kleen
2021-02-12 22:46                   ` Andy Lutomirski
2021-02-13  9:38                   ` Peter Zijlstra
2021-02-12 23:51                 ` Paolo Bonzini
2021-03-23  9:33 ` Joerg Roedel

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