From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A7E9C433E0 for ; Sun, 21 Feb 2021 18:24:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 445AA64EE9 for ; Sun, 21 Feb 2021 18:24:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230107AbhBUSYr (ORCPT ); Sun, 21 Feb 2021 13:24:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229807AbhBUSYp (ORCPT ); Sun, 21 Feb 2021 13:24:45 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81F85C061574; Sun, 21 Feb 2021 10:24:05 -0800 (PST) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECBD2BB2; Sun, 21 Feb 2021 19:24:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1613931844; bh=orousB+kOMLJsWZCvVHsBnccCXT5Cw7mZo7av0LIF8o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=wB6H8dAsvUMP7HUZKu5ZvNAtM49Zsy6DTGALbPMQh/6+5lMdTGFsls0KeJEunQtTR FfcpXAHVstN1ruLTTrBcJ+H+8KIZybo2eBjmomtz0W0uGx0Ta+t0mWvC/dCtlr6ofs kAJ90Er6X6Qjeru1iqmShQf2cRm/lCsfN5Fikndw= Date: Sun, 21 Feb 2021 20:23:37 +0200 From: Laurent Pinchart To: Lyude Paul Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, nouveau@lists.freedesktop.org, Ville =?utf-8?B?U3lyasOkbMOk?= , Jani Nikula , Rodrigo Vivi , Thomas Zimmermann , Alex Deucher , Christian =?utf-8?B?S8O2bmln?= , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Joonas Lahtinen , Rob Clark , Sean Paul , Hyun Kwon , Michal Simek , Luben Tuikov , Jeevan B , Emil Velikov , Oleg Vasilev , Imre Deak , Manasi Navare , =?utf-8?B?Sm9zw6k=?= Roberto de Souza , Kuogee Hsieh , Stephen Boyd , Tanmay Shah , Lee Jones , Chandan Uddaraju , open list , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: Re: [PATCH 20/30] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() Message-ID: References: <20210219215326.2227596-1-lyude@redhat.com> <20210219215326.2227596-21-lyude@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210219215326.2227596-21-lyude@redhat.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Lyude, Thank you for the patch. On Fri, Feb 19, 2021 at 04:53:16PM -0500, Lyude Paul wrote: > So that we can start using drm_dbg_*() for > drm_dp_link_train_channel_eq_delay() and > drm_dp_lttpr_link_train_channel_eq_delay(). > > Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 14 +++++++++----- > .../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++-- > drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++-- > drivers/gpu/drm/radeon/atombios_dp.c | 2 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- > include/drm/drm_dp_helper.h | 6 ++++-- > 8 files changed, 22 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > index 4468f9d6b4dd..59ce6f620fdc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > @@ -676,7 +676,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index ce08eb3bface..a9316c1ecb52 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > -static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > +static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + unsigned long rd_interval) > { > if (rd_interval > 4) > DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", > @@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > usleep_range(rd_interval, rd_interval * 2); > } > > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + __drm_dp_link_train_channel_eq_delay(aux, > + dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > DP_TRAINING_AUX_RD_MASK); > } > EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); > @@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) > return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; > } > > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > { > u8 interval = dp_lttpr_phy_cap(phy_cap, > DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & > DP_TRAINING_AUX_RD_MASK; > > - __drm_dp_link_train_channel_eq_delay(interval); > + __drm_dp_link_train_channel_eq_delay(aux, interval); > } > EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 222073d46bdb..fe8b5a5d9d1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -593,11 +593,11 @@ intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, > enum drm_dp_phy dp_phy) > { > if (dp_phy == DP_PHY_DPRX) { > - drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); > } else { > const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); > > - drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); > + drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps); > } > } > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 2501a6b326a3..33df288dd4eb 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) > static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) > { > dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > } > > static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > @@ -1215,7 +1215,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); > > for (tries = 0; tries <= maximum_retries; tries++) { > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > > ret = dp_ctrl_read_link_status(ctrl, link_status); > if (ret) > diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c > index 6501598448b4..4fb397ee7c84 100644 > --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c > +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c > @@ -665,7 +665,7 @@ static int edp_start_link_train_2(struct edp_ctrl *ctrl) > return ret; > > while (1) { > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); > if (rlen < DP_LINK_STATUS_SIZE) { > @@ -743,7 +743,7 @@ static int edp_clear_training_pattern(struct edp_ctrl *ctrl) > > ret = edp_train_pattern_set_write(ctrl, 0); > > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > return ret; > } > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index 299b9d8da376..4c1e551d9714 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -743,7 +743,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 5cc295d8ba9f..f6f2293db18d 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -778,7 +778,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) > if (ret) > return ret; > > - drm_dp_link_train_channel_eq_delay(dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); > ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); > if (ret < 0) > return ret; > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e4681665231e..2151aeb6c279 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1479,8 +1479,10 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_clock_recovery_delay(void); > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94883C433E0 for ; Sun, 21 Feb 2021 18:24:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45B0064E67 for ; Sun, 21 Feb 2021 18:24:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 45B0064E67 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=nouveau-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A34C46E42A; Sun, 21 Feb 2021 18:24:06 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 946C66E426; Sun, 21 Feb 2021 18:24:05 +0000 (UTC) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECBD2BB2; Sun, 21 Feb 2021 19:24:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1613931844; bh=orousB+kOMLJsWZCvVHsBnccCXT5Cw7mZo7av0LIF8o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=wB6H8dAsvUMP7HUZKu5ZvNAtM49Zsy6DTGALbPMQh/6+5lMdTGFsls0KeJEunQtTR FfcpXAHVstN1ruLTTrBcJ+H+8KIZybo2eBjmomtz0W0uGx0Ta+t0mWvC/dCtlr6ofs kAJ90Er6X6Qjeru1iqmShQf2cRm/lCsfN5Fikndw= Date: Sun, 21 Feb 2021 20:23:37 +0200 From: Laurent Pinchart To: Lyude Paul Message-ID: References: <20210219215326.2227596-1-lyude@redhat.com> <20210219215326.2227596-21-lyude@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210219215326.2227596-21-lyude@redhat.com> Subject: Re: [Nouveau] [PATCH 20/30] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() X-BeenThere: nouveau@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Nouveau development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , nouveau@lists.freedesktop.org, Imre Deak , Joonas Lahtinen , Oleg Vasilev , dri-devel@lists.freedesktop.org, Lee Jones , Ville =?utf-8?B?U3lyasOkbMOk?= , Emil Velikov , Michal Simek , amd-gfx@lists.freedesktop.org, Luben Tuikov , Chandan Uddaraju , Daniel Vetter , Jeevan B , "open list:DRM DRIVER FOR MSM ADRENO GPU" , intel-gfx@lists.freedesktop.org, Maarten Lankhorst , Maxime Ripard , Stephen Boyd , Kuogee Hsieh , Jani Nikula , Rodrigo Vivi , =?utf-8?B?Sm9zw6k=?= Roberto de Souza , Sean Paul , "moderated list:ARM/ZYNQ ARCHITECTURE" , Tanmay Shah , Hyun Kwon , open list , Manasi Navare , Rob Clark , Alex Deucher , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Christian =?utf-8?B?S8O2bmln?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: nouveau-bounces@lists.freedesktop.org Sender: "Nouveau" Hi Lyude, Thank you for the patch. On Fri, Feb 19, 2021 at 04:53:16PM -0500, Lyude Paul wrote: > So that we can start using drm_dbg_*() for > drm_dp_link_train_channel_eq_delay() and > drm_dp_lttpr_link_train_channel_eq_delay(). > > Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 14 +++++++++----- > .../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++-- > drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++-- > drivers/gpu/drm/radeon/atombios_dp.c | 2 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- > include/drm/drm_dp_helper.h | 6 ++++-- > 8 files changed, 22 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > index 4468f9d6b4dd..59ce6f620fdc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > @@ -676,7 +676,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index ce08eb3bface..a9316c1ecb52 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > -static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > +static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + unsigned long rd_interval) > { > if (rd_interval > 4) > DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", > @@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > usleep_range(rd_interval, rd_interval * 2); > } > > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + __drm_dp_link_train_channel_eq_delay(aux, > + dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > DP_TRAINING_AUX_RD_MASK); > } > EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); > @@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) > return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; > } > > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > { > u8 interval = dp_lttpr_phy_cap(phy_cap, > DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & > DP_TRAINING_AUX_RD_MASK; > > - __drm_dp_link_train_channel_eq_delay(interval); > + __drm_dp_link_train_channel_eq_delay(aux, interval); > } > EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 222073d46bdb..fe8b5a5d9d1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -593,11 +593,11 @@ intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, > enum drm_dp_phy dp_phy) > { > if (dp_phy == DP_PHY_DPRX) { > - drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); > } else { > const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); > > - drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); > + drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps); > } > } > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 2501a6b326a3..33df288dd4eb 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) > static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) > { > dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > } > > static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > @@ -1215,7 +1215,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); > > for (tries = 0; tries <= maximum_retries; tries++) { > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > > ret = dp_ctrl_read_link_status(ctrl, link_status); > if (ret) > diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c > index 6501598448b4..4fb397ee7c84 100644 > --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c > +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c > @@ -665,7 +665,7 @@ static int edp_start_link_train_2(struct edp_ctrl *ctrl) > return ret; > > while (1) { > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); > if (rlen < DP_LINK_STATUS_SIZE) { > @@ -743,7 +743,7 @@ static int edp_clear_training_pattern(struct edp_ctrl *ctrl) > > ret = edp_train_pattern_set_write(ctrl, 0); > > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > return ret; > } > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index 299b9d8da376..4c1e551d9714 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -743,7 +743,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 5cc295d8ba9f..f6f2293db18d 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -778,7 +778,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) > if (ret) > return ret; > > - drm_dp_link_train_channel_eq_delay(dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); > ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); > if (ret < 0) > return ret; > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e4681665231e..2151aeb6c279 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1479,8 +1479,10 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_clock_recovery_delay(void); > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); -- Regards, Laurent Pinchart _______________________________________________ Nouveau mailing list Nouveau@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/nouveau From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 387E4C433DB for ; Sun, 21 Feb 2021 18:25:15 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB17964EE9 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Lyude, Thank you for the patch. On Fri, Feb 19, 2021 at 04:53:16PM -0500, Lyude Paul wrote: > So that we can start using drm_dbg_*() for > drm_dp_link_train_channel_eq_delay() and > drm_dp_lttpr_link_train_channel_eq_delay(). > > Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 14 +++++++++----- > .../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++-- > drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++-- > drivers/gpu/drm/radeon/atombios_dp.c | 2 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- > include/drm/drm_dp_helper.h | 6 ++++-- > 8 files changed, 22 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > index 4468f9d6b4dd..59ce6f620fdc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > @@ -676,7 +676,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index ce08eb3bface..a9316c1ecb52 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > -static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > +static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + unsigned long rd_interval) > { > if (rd_interval > 4) > DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", > @@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > usleep_range(rd_interval, rd_interval * 2); > } > > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + __drm_dp_link_train_channel_eq_delay(aux, > + dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > DP_TRAINING_AUX_RD_MASK); > } > EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); > @@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) > return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; > } > > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > { > u8 interval = dp_lttpr_phy_cap(phy_cap, > DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & > DP_TRAINING_AUX_RD_MASK; > > - __drm_dp_link_train_channel_eq_delay(interval); > + __drm_dp_link_train_channel_eq_delay(aux, interval); > } > EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 222073d46bdb..fe8b5a5d9d1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -593,11 +593,11 @@ intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, > enum drm_dp_phy dp_phy) > { > if (dp_phy == DP_PHY_DPRX) { > - drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); > } else { > const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); > > - drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); > + drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps); > } > } > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 2501a6b326a3..33df288dd4eb 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) > static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) > { > dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > } > > static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > @@ -1215,7 +1215,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); > > for (tries = 0; tries <= maximum_retries; tries++) { > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > > ret = dp_ctrl_read_link_status(ctrl, link_status); > if (ret) > diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c > index 6501598448b4..4fb397ee7c84 100644 > --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c > +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c > @@ -665,7 +665,7 @@ static int edp_start_link_train_2(struct edp_ctrl *ctrl) > return ret; > > while (1) { > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); > if (rlen < DP_LINK_STATUS_SIZE) { > @@ -743,7 +743,7 @@ static int edp_clear_training_pattern(struct edp_ctrl *ctrl) > > ret = edp_train_pattern_set_write(ctrl, 0); > > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > return ret; > } > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index 299b9d8da376..4c1e551d9714 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -743,7 +743,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 5cc295d8ba9f..f6f2293db18d 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -778,7 +778,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) > if (ret) > return ret; > > - drm_dp_link_train_channel_eq_delay(dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); > ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); > if (ret < 0) > return ret; > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e4681665231e..2151aeb6c279 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1479,8 +1479,10 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_clock_recovery_delay(void); > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); -- Regards, Laurent Pinchart _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 590D5C433E9 for ; Sun, 21 Feb 2021 18:24:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13FA664EE9 for ; Sun, 21 Feb 2021 18:24:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 13FA664EE9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C868A6E42F; Sun, 21 Feb 2021 18:24:06 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 946C66E426; Sun, 21 Feb 2021 18:24:05 +0000 (UTC) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECBD2BB2; Sun, 21 Feb 2021 19:24:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1613931844; bh=orousB+kOMLJsWZCvVHsBnccCXT5Cw7mZo7av0LIF8o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=wB6H8dAsvUMP7HUZKu5ZvNAtM49Zsy6DTGALbPMQh/6+5lMdTGFsls0KeJEunQtTR FfcpXAHVstN1ruLTTrBcJ+H+8KIZybo2eBjmomtz0W0uGx0Ta+t0mWvC/dCtlr6ofs kAJ90Er6X6Qjeru1iqmShQf2cRm/lCsfN5Fikndw= Date: Sun, 21 Feb 2021 20:23:37 +0200 From: Laurent Pinchart To: Lyude Paul Subject: Re: [PATCH 20/30] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() Message-ID: References: <20210219215326.2227596-1-lyude@redhat.com> <20210219215326.2227596-21-lyude@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210219215326.2227596-21-lyude@redhat.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , nouveau@lists.freedesktop.org, Oleg Vasilev , dri-devel@lists.freedesktop.org, Lee Jones , Emil Velikov , Michal Simek , amd-gfx@lists.freedesktop.org, Luben Tuikov , Chandan Uddaraju , "open list:DRM DRIVER FOR MSM ADRENO GPU" , intel-gfx@lists.freedesktop.org, Stephen Boyd , Kuogee Hsieh , Rodrigo Vivi , =?utf-8?B?Sm9zw6k=?= Roberto de Souza , Sean Paul , "moderated list:ARM/ZYNQ ARCHITECTURE" , Tanmay Shah , Hyun Kwon , open list , Manasi Navare , Thomas Zimmermann , Alex Deucher , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Christian =?utf-8?B?S8O2bmln?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Lyude, Thank you for the patch. On Fri, Feb 19, 2021 at 04:53:16PM -0500, Lyude Paul wrote: > So that we can start using drm_dbg_*() for > drm_dp_link_train_channel_eq_delay() and > drm_dp_lttpr_link_train_channel_eq_delay(). > > Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 14 +++++++++----- > .../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++-- > drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++-- > drivers/gpu/drm/radeon/atombios_dp.c | 2 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- > include/drm/drm_dp_helper.h | 6 ++++-- > 8 files changed, 22 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > index 4468f9d6b4dd..59ce6f620fdc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > @@ -676,7 +676,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index ce08eb3bface..a9316c1ecb52 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > -static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > +static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + unsigned long rd_interval) > { > if (rd_interval > 4) > DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", > @@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > usleep_range(rd_interval, rd_interval * 2); > } > > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + __drm_dp_link_train_channel_eq_delay(aux, > + dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > DP_TRAINING_AUX_RD_MASK); > } > EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); > @@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) > return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; > } > > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > { > u8 interval = dp_lttpr_phy_cap(phy_cap, > DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & > DP_TRAINING_AUX_RD_MASK; > > - __drm_dp_link_train_channel_eq_delay(interval); > + __drm_dp_link_train_channel_eq_delay(aux, interval); > } > EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 222073d46bdb..fe8b5a5d9d1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -593,11 +593,11 @@ intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, > enum drm_dp_phy dp_phy) > { > if (dp_phy == DP_PHY_DPRX) { > - drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); > } else { > const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); > > - drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); > + drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps); > } > } > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 2501a6b326a3..33df288dd4eb 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) > static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) > { > dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > } > > static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > @@ -1215,7 +1215,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); > > for (tries = 0; tries <= maximum_retries; tries++) { > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > > ret = dp_ctrl_read_link_status(ctrl, link_status); > if (ret) > diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c > index 6501598448b4..4fb397ee7c84 100644 > --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c > +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c > @@ -665,7 +665,7 @@ static int edp_start_link_train_2(struct edp_ctrl *ctrl) > return ret; > > while (1) { > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); > if (rlen < DP_LINK_STATUS_SIZE) { > @@ -743,7 +743,7 @@ static int edp_clear_training_pattern(struct edp_ctrl *ctrl) > > ret = edp_train_pattern_set_write(ctrl, 0); > > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > return ret; > } > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index 299b9d8da376..4c1e551d9714 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -743,7 +743,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 5cc295d8ba9f..f6f2293db18d 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -778,7 +778,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) > if (ret) > return ret; > > - drm_dp_link_train_channel_eq_delay(dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); > ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); > if (ret < 0) > return ret; > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e4681665231e..2151aeb6c279 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1479,8 +1479,10 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_clock_recovery_delay(void); > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); -- Regards, Laurent Pinchart _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1D6AC433DB for ; Sun, 21 Feb 2021 18:24:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8495E64EEC for ; Sun, 21 Feb 2021 18:24:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8495E64EEC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF5896E431; Sun, 21 Feb 2021 18:24:07 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 946C66E426; Sun, 21 Feb 2021 18:24:05 +0000 (UTC) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECBD2BB2; Sun, 21 Feb 2021 19:24:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1613931844; bh=orousB+kOMLJsWZCvVHsBnccCXT5Cw7mZo7av0LIF8o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=wB6H8dAsvUMP7HUZKu5ZvNAtM49Zsy6DTGALbPMQh/6+5lMdTGFsls0KeJEunQtTR FfcpXAHVstN1ruLTTrBcJ+H+8KIZybo2eBjmomtz0W0uGx0Ta+t0mWvC/dCtlr6ofs kAJ90Er6X6Qjeru1iqmShQf2cRm/lCsfN5Fikndw= Date: Sun, 21 Feb 2021 20:23:37 +0200 From: Laurent Pinchart To: Lyude Paul Message-ID: References: <20210219215326.2227596-1-lyude@redhat.com> <20210219215326.2227596-21-lyude@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210219215326.2227596-21-lyude@redhat.com> Subject: Re: [Intel-gfx] [PATCH 20/30] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , nouveau@lists.freedesktop.org, Oleg Vasilev , dri-devel@lists.freedesktop.org, Lee Jones , Emil Velikov , Michal Simek , amd-gfx@lists.freedesktop.org, Luben Tuikov , Chandan Uddaraju , "open list:DRM DRIVER FOR MSM ADRENO GPU" , intel-gfx@lists.freedesktop.org, Maxime Ripard , Stephen Boyd , Kuogee Hsieh , "moderated list:ARM/ZYNQ ARCHITECTURE" , Tanmay Shah , Hyun Kwon , open list , Thomas Zimmermann , Alex Deucher , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Christian =?utf-8?B?S8O2bmln?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Lyude, Thank you for the patch. On Fri, Feb 19, 2021 at 04:53:16PM -0500, Lyude Paul wrote: > So that we can start using drm_dbg_*() for > drm_dp_link_train_channel_eq_delay() and > drm_dp_lttpr_link_train_channel_eq_delay(). > > Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 14 +++++++++----- > .../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++-- > drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++-- > drivers/gpu/drm/radeon/atombios_dp.c | 2 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- > include/drm/drm_dp_helper.h | 6 ++++-- > 8 files changed, 22 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > index 4468f9d6b4dd..59ce6f620fdc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > @@ -676,7 +676,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index ce08eb3bface..a9316c1ecb52 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > -static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > +static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + unsigned long rd_interval) > { > if (rd_interval > 4) > DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", > @@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > usleep_range(rd_interval, rd_interval * 2); > } > > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + __drm_dp_link_train_channel_eq_delay(aux, > + dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > DP_TRAINING_AUX_RD_MASK); > } > EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); > @@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) > return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; > } > > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > { > u8 interval = dp_lttpr_phy_cap(phy_cap, > DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & > DP_TRAINING_AUX_RD_MASK; > > - __drm_dp_link_train_channel_eq_delay(interval); > + __drm_dp_link_train_channel_eq_delay(aux, interval); > } > EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 222073d46bdb..fe8b5a5d9d1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -593,11 +593,11 @@ intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, > enum drm_dp_phy dp_phy) > { > if (dp_phy == DP_PHY_DPRX) { > - drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); > } else { > const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); > > - drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); > + drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps); > } > } > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 2501a6b326a3..33df288dd4eb 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) > static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) > { > dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > } > > static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > @@ -1215,7 +1215,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); > > for (tries = 0; tries <= maximum_retries; tries++) { > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > > ret = dp_ctrl_read_link_status(ctrl, link_status); > if (ret) > diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c > index 6501598448b4..4fb397ee7c84 100644 > --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c > +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c > @@ -665,7 +665,7 @@ static int edp_start_link_train_2(struct edp_ctrl *ctrl) > return ret; > > while (1) { > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); > if (rlen < DP_LINK_STATUS_SIZE) { > @@ -743,7 +743,7 @@ static int edp_clear_training_pattern(struct edp_ctrl *ctrl) > > ret = edp_train_pattern_set_write(ctrl, 0); > > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > return ret; > } > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index 299b9d8da376..4c1e551d9714 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -743,7 +743,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 5cc295d8ba9f..f6f2293db18d 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -778,7 +778,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) > if (ret) > return ret; > > - drm_dp_link_train_channel_eq_delay(dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); > ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); > if (ret < 0) > return ret; > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e4681665231e..2151aeb6c279 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1479,8 +1479,10 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_clock_recovery_delay(void); > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); -- Regards, Laurent Pinchart _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7487FC433DB for ; Sun, 21 Feb 2021 18:24:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03B4A64EE9 for ; Sun, 21 Feb 2021 18:24:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03B4A64EE9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=amd-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 85CD26E426; Sun, 21 Feb 2021 18:24:06 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id 946C66E426; Sun, 21 Feb 2021 18:24:05 +0000 (UTC) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id ECBD2BB2; Sun, 21 Feb 2021 19:24:03 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1613931844; bh=orousB+kOMLJsWZCvVHsBnccCXT5Cw7mZo7av0LIF8o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=wB6H8dAsvUMP7HUZKu5ZvNAtM49Zsy6DTGALbPMQh/6+5lMdTGFsls0KeJEunQtTR FfcpXAHVstN1ruLTTrBcJ+H+8KIZybo2eBjmomtz0W0uGx0Ta+t0mWvC/dCtlr6ofs kAJ90Er6X6Qjeru1iqmShQf2cRm/lCsfN5Fikndw= Date: Sun, 21 Feb 2021 20:23:37 +0200 From: Laurent Pinchart To: Lyude Paul Subject: Re: [PATCH 20/30] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() Message-ID: References: <20210219215326.2227596-1-lyude@redhat.com> <20210219215326.2227596-21-lyude@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210219215326.2227596-21-lyude@redhat.com> X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , nouveau@lists.freedesktop.org, Imre Deak , Joonas Lahtinen , Oleg Vasilev , dri-devel@lists.freedesktop.org, Lee Jones , Ville =?utf-8?B?U3lyasOkbMOk?= , Emil Velikov , Michal Simek , amd-gfx@lists.freedesktop.org, Luben Tuikov , Chandan Uddaraju , Daniel Vetter , Jeevan B , "open list:DRM DRIVER FOR MSM ADRENO GPU" , intel-gfx@lists.freedesktop.org, Maarten Lankhorst , Maxime Ripard , Stephen Boyd , Kuogee Hsieh , Jani Nikula , Rodrigo Vivi , =?utf-8?B?Sm9zw6k=?= Roberto de Souza , Sean Paul , "moderated list:ARM/ZYNQ ARCHITECTURE" , Tanmay Shah , Hyun Kwon , open list , Manasi Navare , Rob Clark , Thomas Zimmermann , Alex Deucher , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Christian =?utf-8?B?S8O2bmln?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Hi Lyude, Thank you for the patch. On Fri, Feb 19, 2021 at 04:53:16PM -0500, Lyude Paul wrote: > So that we can start using drm_dbg_*() for > drm_dp_link_train_channel_eq_delay() and > drm_dp_lttpr_link_train_channel_eq_delay(). > > Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart > --- > drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- > drivers/gpu/drm/drm_dp_helper.c | 14 +++++++++----- > .../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++-- > drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++-- > drivers/gpu/drm/radeon/atombios_dp.c | 2 +- > drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- > include/drm/drm_dp_helper.h | 6 ++++-- > 8 files changed, 22 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > index 4468f9d6b4dd..59ce6f620fdc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c > @@ -676,7 +676,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index ce08eb3bface..a9316c1ecb52 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > } > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); > > -static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > +static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + unsigned long rd_interval) > { > if (rd_interval > 4) > DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", > @@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) > usleep_range(rd_interval, rd_interval * 2); > } > > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) > { > - __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > + __drm_dp_link_train_channel_eq_delay(aux, > + dpcd[DP_TRAINING_AUX_RD_INTERVAL] & > DP_TRAINING_AUX_RD_MASK); > } > EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); > @@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) > return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; > } > > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) > { > u8 interval = dp_lttpr_phy_cap(phy_cap, > DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & > DP_TRAINING_AUX_RD_MASK; > > - __drm_dp_link_train_channel_eq_delay(interval); > + __drm_dp_link_train_channel_eq_delay(aux, interval); > } > EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > index 222073d46bdb..fe8b5a5d9d1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c > @@ -593,11 +593,11 @@ intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, > enum drm_dp_phy dp_phy) > { > if (dp_phy == DP_PHY_DPRX) { > - drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); > } else { > const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); > > - drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); > + drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps); > } > } > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 2501a6b326a3..33df288dd4eb 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) > static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) > { > dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > } > > static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > @@ -1215,7 +1215,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); > > for (tries = 0; tries <= maximum_retries; tries++) { > - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); > > ret = dp_ctrl_read_link_status(ctrl, link_status); > if (ret) > diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c > index 6501598448b4..4fb397ee7c84 100644 > --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c > +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c > @@ -665,7 +665,7 @@ static int edp_start_link_train_2(struct edp_ctrl *ctrl) > return ret; > > while (1) { > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); > if (rlen < DP_LINK_STATUS_SIZE) { > @@ -743,7 +743,7 @@ static int edp_clear_training_pattern(struct edp_ctrl *ctrl) > > ret = edp_train_pattern_set_write(ctrl, 0); > > - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); > + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); > > return ret; > } > diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c > index 299b9d8da376..4c1e551d9714 100644 > --- a/drivers/gpu/drm/radeon/atombios_dp.c > +++ b/drivers/gpu/drm/radeon/atombios_dp.c > @@ -743,7 +743,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) > dp_info->tries = 0; > channel_eq = false; > while (1) { > - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); > + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); > > if (drm_dp_dpcd_read_link_status(dp_info->aux, > dp_info->link_status) <= 0) { > diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c > index 5cc295d8ba9f..f6f2293db18d 100644 > --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c > +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c > @@ -778,7 +778,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) > if (ret) > return ret; > > - drm_dp_link_train_channel_eq_delay(dp->dpcd); > + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); > ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); > if (ret < 0) > return ret; > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index e4681665231e..2151aeb6c279 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1479,8 +1479,10 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ > void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, > const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > void drm_dp_lttpr_link_train_clock_recovery_delay(void); > -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); > +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, > + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > u8 drm_dp_link_rate_to_bw_code(int link_rate); > int drm_dp_bw_code_to_link_rate(u8 link_bw); -- Regards, Laurent Pinchart _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx