From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F09E6C433DB for ; Fri, 26 Feb 2021 17:25:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A48CB64F1B for ; Fri, 26 Feb 2021 17:25:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229894AbhBZRZh (ORCPT ); Fri, 26 Feb 2021 12:25:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229545AbhBZRZg (ORCPT ); Fri, 26 Feb 2021 12:25:36 -0500 Received: from mail-ot1-x32c.google.com (mail-ot1-x32c.google.com [IPv6:2607:f8b0:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92FAFC06174A for ; Fri, 26 Feb 2021 09:24:55 -0800 (PST) Received: by mail-ot1-x32c.google.com with SMTP id s3so9734813otg.5 for ; Fri, 26 Feb 2021 09:24:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=46MifqQE4f/PAS/QIgiSzbDRBfO/hWIxYDCH5F8gOGo=; b=h6LA10EZslChayy3Ur3LXT2ugyZAipLvkbzRswQ2gMM8RTpMC49WQpw317mvKPkbKN cGggGXn06t6hx19TERjXoLlIDHfz7WFiDxk8qwla7OsM0Qwdc++LfVLlXrF5Z7ukbm5/ alyMQyCoFDUcHcSjRSXUwPrpkxYypingOrvvN80bnpImQYs/vSWL2Pr5GsqfmRzwjVWj hDFkdPU6+RV8kpxyPIDjBQHN0e1yZL5f2KdfOufP9nw9t9i0nlFS0raBKIA2Hxf/N8TC YSjQiMadpDWhTgmlTHaJd3/2eUCRXs+nqnCYrRfPW5CQxlV/WfzYBT26Uu53MlTOiz7v yLYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=46MifqQE4f/PAS/QIgiSzbDRBfO/hWIxYDCH5F8gOGo=; b=LMJIKVDXmPdI7md1ztNL7XYLY/HDG37JH/7B3uVEbB75T+AbCOGxYzwkKTpBAgjXlI L705MeK9Ec2aoRrqKkCHCGPfx25hX+N1wHk8PO4T9MDIzCjDwyARSqr8RkTHOX1AE+YP FjC+UftFCGVXVHr8HHOZ1J6P7VXZn8+vb5SCzhOW7veKLk9TmxZ2zlCOQyzYMG5ED3bV MPpilBARvNnZWpu/qKOGxdhs8jBPeSwUx5xhEB8zWQ56FKHQK7g+tvg5xvVny9pwxDaX AdI9lRQc1vzx1AImK/2xh7Bsw1/hAo57D72WIFy6d4lJZgt5eM5JOEuwNqEcJn5RducO mAuQ== X-Gm-Message-State: AOAM533JZEKDOFEkj4KeWSJXlwd0kGQyW1U9blokcEZaDnmaKUr6hEWW IyHuH0pQPf1EMKRp5slRIBr/Yg== X-Google-Smtp-Source: ABdhPJz7cnRLcAi6rf0O0EbFSNRRU54HnjS36fldgfxWOIO06Ym10eHK8rx7//LE2c+AXwiJM8G3ug== X-Received: by 2002:a05:6830:232f:: with SMTP id q15mr3180613otg.165.1614360294902; Fri, 26 Feb 2021 09:24:54 -0800 (PST) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id e17sm1938869otl.75.2021.02.26.09.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 09:24:54 -0800 (PST) Date: Fri, 26 Feb 2021 11:24:52 -0600 From: Bjorn Andersson To: Sai Prakash Ranjan Cc: Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , Akhil P Oommen , iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCHv2 2/2] iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote: > Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU > both implement "arm,mmu-500" in some QTI SoCs and to run through > adreno smmu specific implementation such as enabling split pagetables > support, we need to match the "qcom,adreno-smmu" compatible first > before apss smmu or else we will be running apps smmu implementation > for adreno smmu and the additional features for adreno smmu is never > set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps > and adreno smmu implementing "arm,mmu-500", so the adreno smmu > implementation is never reached because the current sequence checks > for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that > specific impl and we never reach adreno smmu specific implementation. > So you're saying that you have a single SMMU instance that's compatible with both an entry in qcom_smmu_impl_of_match[] and "qcom,adreno-smmu"? Per your proposed change we will pick the adreno ops _only_ for this component, essentially disabling the non-Adreno quirks selected by the qcom impl. As such keeping the non-adreno compatible in the qcom_smmu_impl_init[] seems to only serve to obfuscate the situation. Don't we somehow need the combined set of quirks? (At least if we're running this with a standard UEFI based boot flow?) Regards, Bjorn > Suggested-by: Akhil P Oommen > Signed-off-by: Sai Prakash Ranjan > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bea3ee0dabc2..03f048aebb80 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > { > const struct device_node *np = smmu->dev->of_node; > > - if (of_match_node(qcom_smmu_impl_of_match, np)) > - return qcom_smmu_create(smmu, &qcom_smmu_impl); > - > + /* > + * Do not change this order of implementation, i.e., first adreno > + * smmu impl and then apss smmu since we can have both implementing > + * arm,mmu-500 in which case we will miss setting adreno smmu specific > + * features if the order is changed. > + */ > if (of_device_is_compatible(np, "qcom,adreno-smmu")) > return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > > + if (of_match_node(qcom_smmu_impl_of_match, np)) > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > + > return smmu; > } > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23E67C433DB for ; Fri, 26 Feb 2021 17:25:01 +0000 (UTC) Received: from smtp1.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9723264F17 for ; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id e17sm1938869otl.75.2021.02.26.09.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 09:24:54 -0800 (PST) Date: Fri, 26 Feb 2021 11:24:52 -0600 From: Bjorn Andersson To: Sai Prakash Ranjan Subject: Re: [PATCHv2 2/2] iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: Will Deacon , Akhil P Oommen , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jordan Crouse , linux-arm-msm@vger.kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote: > Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU > both implement "arm,mmu-500" in some QTI SoCs and to run through > adreno smmu specific implementation such as enabling split pagetables > support, we need to match the "qcom,adreno-smmu" compatible first > before apss smmu or else we will be running apps smmu implementation > for adreno smmu and the additional features for adreno smmu is never > set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps > and adreno smmu implementing "arm,mmu-500", so the adreno smmu > implementation is never reached because the current sequence checks > for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that > specific impl and we never reach adreno smmu specific implementation. > So you're saying that you have a single SMMU instance that's compatible with both an entry in qcom_smmu_impl_of_match[] and "qcom,adreno-smmu"? Per your proposed change we will pick the adreno ops _only_ for this component, essentially disabling the non-Adreno quirks selected by the qcom impl. As such keeping the non-adreno compatible in the qcom_smmu_impl_init[] seems to only serve to obfuscate the situation. Don't we somehow need the combined set of quirks? (At least if we're running this with a standard UEFI based boot flow?) Regards, Bjorn > Suggested-by: Akhil P Oommen > Signed-off-by: Sai Prakash Ranjan > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bea3ee0dabc2..03f048aebb80 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > { > const struct device_node *np = smmu->dev->of_node; > > - if (of_match_node(qcom_smmu_impl_of_match, np)) > - return qcom_smmu_create(smmu, &qcom_smmu_impl); > - > + /* > + * Do not change this order of implementation, i.e., first adreno > + * smmu impl and then apss smmu since we can have both implementing > + * arm,mmu-500 in which case we will miss setting adreno smmu specific > + * features if the order is changed. > + */ > if (of_device_is_compatible(np, "qcom,adreno-smmu")) > return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > > + if (of_match_node(qcom_smmu_impl_of_match, np)) > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > + > return smmu; > } > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4222C433DB for ; Fri, 26 Feb 2021 17:26:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6406260202 for ; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id e17sm1938869otl.75.2021.02.26.09.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Feb 2021 09:24:54 -0800 (PST) Date: Fri, 26 Feb 2021 11:24:52 -0600 From: Bjorn Andersson To: Sai Prakash Ranjan Subject: Re: [PATCHv2 2/2] iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210226_122458_928801_9E6FA513 X-CRM114-Status: GOOD ( 24.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Will Deacon , Joerg Roedel , Akhil P Oommen , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Jordan Crouse , linux-arm-msm@vger.kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote: > Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU > both implement "arm,mmu-500" in some QTI SoCs and to run through > adreno smmu specific implementation such as enabling split pagetables > support, we need to match the "qcom,adreno-smmu" compatible first > before apss smmu or else we will be running apps smmu implementation > for adreno smmu and the additional features for adreno smmu is never > set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps > and adreno smmu implementing "arm,mmu-500", so the adreno smmu > implementation is never reached because the current sequence checks > for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that > specific impl and we never reach adreno smmu specific implementation. > So you're saying that you have a single SMMU instance that's compatible with both an entry in qcom_smmu_impl_of_match[] and "qcom,adreno-smmu"? Per your proposed change we will pick the adreno ops _only_ for this component, essentially disabling the non-Adreno quirks selected by the qcom impl. As such keeping the non-adreno compatible in the qcom_smmu_impl_init[] seems to only serve to obfuscate the situation. Don't we somehow need the combined set of quirks? (At least if we're running this with a standard UEFI based boot flow?) Regards, Bjorn > Suggested-by: Akhil P Oommen > Signed-off-by: Sai Prakash Ranjan > --- > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bea3ee0dabc2..03f048aebb80 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > { > const struct device_node *np = smmu->dev->of_node; > > - if (of_match_node(qcom_smmu_impl_of_match, np)) > - return qcom_smmu_create(smmu, &qcom_smmu_impl); > - > + /* > + * Do not change this order of implementation, i.e., first adreno > + * smmu impl and then apss smmu since we can have both implementing > + * arm,mmu-500 in which case we will miss setting adreno smmu specific > + * features if the order is changed. > + */ > if (of_device_is_compatible(np, "qcom,adreno-smmu")) > return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > > + if (of_match_node(qcom_smmu_impl_of_match, np)) > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > + > return smmu; > } > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel