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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id v7sm70768otq.62.2021.03.10.10.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 10:13:05 -0800 (PST) Date: Wed, 10 Mar 2021 12:13:04 -0600 From: Bjorn Andersson To: Shawn Guo Cc: Linus Walleij , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v2] pinctrl: qcom: support gpio_chip .set_config call Message-ID: References: <20210303131858.3976-1-shawn.guo@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210303131858.3976-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 03 Mar 07:18 CST 2021, Shawn Guo wrote: > In case of ACPI boot, GPIO core does the right thing to parse GPIO pin > configs from ACPI table, and call into gpio_chip's .set_config hook for > setting them up. It enables such support on qcom platform by using > generic config function, which in turn calls into .pin_config_set of > pinconf for setting up hardware. For qcom platform, it's possible to > reuse pin group config functions for pin config hooks, because every pin > is maintained as a single group. > > This change fixes the problem that Touchpad of Lenovo Flex 5G laptop > doesn't work with ACPI boot, because PullUp config of Touchpad GpioInt > pin is not set up by the kernel. > Per Linus comment that this is how others are doing it, I guess we can do it too... Acked-by: Bjorn Andersson Regards, Bjorn > Signed-off-by: Shawn Guo > --- > Changes for v2: > - Add pin config functions that simply call into group config ones. > > drivers/pinctrl/qcom/pinctrl-msm.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index af6ed7f43058..a59bb4cbd97e 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -489,10 +489,24 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, > return 0; > } > > +static int msm_config_pin_get(struct pinctrl_dev *pctldev, unsigned int pin, > + unsigned long *config) > +{ > + return msm_config_group_get(pctldev, pin, config); > +} > + > +static int msm_config_pin_set(struct pinctrl_dev *pctldev, unsigned pin, > + unsigned long *configs, unsigned num_configs) > +{ > + return msm_config_group_set(pctldev, pin, configs, num_configs); > +} > + > static const struct pinconf_ops msm_pinconf_ops = { > .is_generic = true, > .pin_config_group_get = msm_config_group_get, > .pin_config_group_set = msm_config_group_set, > + .pin_config_get = msm_config_pin_get, > + .pin_config_set = msm_config_pin_set, > }; > > static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) > @@ -717,6 +731,7 @@ static const struct gpio_chip msm_gpio_template = { > .get_direction = msm_gpio_get_direction, > .get = msm_gpio_get, > .set = msm_gpio_set, > + .set_config = gpiochip_generic_config, > .request = gpiochip_generic_request, > .free = gpiochip_generic_free, > .dbg_show = msm_gpio_dbg_show, > -- > 2.17.1 >