From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4066EC433E0 for ; Tue, 23 Mar 2021 10:52:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01632619C4 for ; Tue, 23 Mar 2021 10:52:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230357AbhCWKwG (ORCPT ); Tue, 23 Mar 2021 06:52:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229728AbhCWKve (ORCPT ); Tue, 23 Mar 2021 06:51:34 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEBD6C061574 for ; Tue, 23 Mar 2021 03:51:32 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id z2so20276104wrl.5 for ; Tue, 23 Mar 2021 03:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=+Rm0Eb8opKfQYfpYJDV6Y/tLoSsGpuasG3Yqocn/+wk=; b=V460lnV5MQidZ9drlcjju5WKgJWJ4lnAjSvh4/bhA7gqTaBNKu/P50bMFcOlFlrU7g 3P86p+Fu68NyIPOW6b4N8XvzWPnCOTY6oZwtBN2Wf+NgPRcoOPEXv09i7CGCthKYzz7Q +2bT1OTMMIFjDijjUEbJzYNAI2vPkJKcx9en6iPxWyCstDTPrAZK/0H+aaqxy7mtozAY 50RoU1cq+m0ZD6XgKgFW0T9uHDQvo1V1SjLjjDCd6CRjw8ljVzwPH7DUOTdB5hVFWKQL MF7jHtAqOqvXQrpLdx5fWEgKm/rKTmC/YjI/QejxGrLeDYZHCag93xqYU640uNPkcZuZ /AUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=+Rm0Eb8opKfQYfpYJDV6Y/tLoSsGpuasG3Yqocn/+wk=; b=VHIjTunal9gbSg0/USudmQOLH8GeHDrpMX5dlFflubq4KxpFKJVFdDrOmvGb17oeOu 0w8CxuLlOcsK1NkjKrrOX9szyMJc9nSwjqqAXnhTqGAEg0vGtK8hvQ4J1NTXUAU8te2Q xke2wn+kH8oG4oabDBbYCnaZVShjoQwYMRUQD3PG/K2Ue5R+70GPUrbQN6zGi0I6pZj8 o9Gz/Hcv6bkE10EXBsZ2aSEdA+jD2S48vtTpgbgO4lPKeyJkk6naxDCKKcdVlq6+UF6g n/1A6+nuT9jTKAce3R567GWDicYxGKzvLfZbeQOxFzdrWIW38BxeJNdQzpHw76ztjR5t vtUQ== X-Gm-Message-State: AOAM5309FFdNMgLN4Z/EtasXZAk3ouZ4Y0Bjc9NmLbxO7cVhKzW6Apzp 91MyR1PEKA8QIAo7GchLT9tSVA== X-Google-Smtp-Source: ABdhPJyEzvSO/OvPPWnDWPmPBfRqF7mbRvT971F7XWqd4tOlJNGs3xw7PhQkeJHkjfLb3M4W8l8jRg== X-Received: by 2002:adf:fb0b:: with SMTP id c11mr3314660wrr.425.1616496691557; Tue, 23 Mar 2021 03:51:31 -0700 (PDT) Received: from myrica ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id s16sm22887746wru.91.2021.03.23.03.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 03:51:31 -0700 (PDT) Date: Tue, 23 Mar 2021 11:51:13 +0100 From: Jean-Philippe Brucker To: Lu Baolu Cc: joro@8bytes.org, will@kernel.org, lorenzo.pieralisi@arm.com, robh+dt@kernel.org, guohanjun@huawei.com, sudeep.holla@arm.com, rjw@rjwysocki.net, lenb@kernel.org, robin.murphy@arm.com, Jonathan.Cameron@huawei.com, eric.auger@redhat.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-accelerators@lists.ozlabs.org, jacob.jun.pan@linux.intel.com, kevin.tian@intel.com, vdumpa@nvidia.com, zhangfei.gao@linaro.org, shameerali.kolothum.thodi@huawei.com, vivek.gautam@arm.com, zhukeqian1@huawei.com, wangzhou1@hisilicon.com, Ashok Raj Subject: Re: [PATCH v13 06/10] iommu: Add a page fault handler Message-ID: References: <20210302092644.2553014-1-jean-philippe@linaro.org> <20210302092644.2553014-7-jean-philippe@linaro.org> <15ff4704-0fbd-243f-8e49-a9523ae63ce6@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <15ff4704-0fbd-243f-8e49-a9523ae63ce6@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Wed, Mar 03, 2021 at 01:27:34PM +0800, Lu Baolu wrote: > I have tested this framework with the Intel VT-d implementation. It > works as expected. Hence, > > Reviewed-by: Lu Baolu > Tested-by: Lu Baolu Thanks! > One possible future optimization is that we could allow the system > administrators to choose between handle PRQs in a workqueue or handle > them synchronously. One research discovered that most of the software > latency of handling a single page fault exists in the schedule part. > Hence, synchronous processing will get shorter software latency if PRQs > are rare and limited. Yes, the risk is that processing a fault synchronously will take too much time, leading to PRI queue overflow if the IOMMU keeps receiving page faults. That's why I opted for the workqueue initially, but it's definitely something we can tweak Thanks, Jean From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_RED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4FF6C433DB for ; Tue, 23 Mar 2021 10:51:37 +0000 (UTC) Received: from smtp2.osuosl.org (smtp2.osuosl.org [140.211.166.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7152A619BA for ; Tue, 23 Mar 2021 10:51:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7152A619BA Authentication-Results: mail.kernel.org; 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Tue, 23 Mar 2021 03:51:31 -0700 (PDT) Received: from myrica ([2001:1715:4e26:a7e0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id s16sm22887746wru.91.2021.03.23.03.51.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Mar 2021 03:51:31 -0700 (PDT) Date: Tue, 23 Mar 2021 11:51:13 +0100 From: Jean-Philippe Brucker To: Lu Baolu Subject: Re: [PATCH v13 06/10] iommu: Add a page fault handler Message-ID: References: <20210302092644.2553014-1-jean-philippe@linaro.org> <20210302092644.2553014-7-jean-philippe@linaro.org> <15ff4704-0fbd-243f-8e49-a9523ae63ce6@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <15ff4704-0fbd-243f-8e49-a9523ae63ce6@linux.intel.com> Cc: vivek.gautam@arm.com, guohanjun@huawei.com, will@kernel.org, Ashok Raj , linux-acpi@vger.kernel.org, zhangfei.gao@linaro.org, lenb@kernel.org, devicetree@vger.kernel.org, kevin.tian@intel.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, rjw@rjwysocki.net, iommu@lists.linux-foundation.org, sudeep.holla@arm.com, robin.murphy@arm.com, linux-accelerators@lists.ozlabs.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, Mar 03, 2021 at 01:27:34PM +0800, Lu Baolu wrote: > I have tested this framework with the Intel VT-d implementation. It > works as expected. Hence, > > Reviewed-by: Lu Baolu > Tested-by: Lu Baolu Thanks! > One possible future optimization is that we could allow the system > administrators to choose between handle PRQs in a workqueue or handle > them synchronously. One research discovered that most of the software > latency of handling a single page fault exists in the schedule part. > Hence, synchronous processing will get shorter software latency if PRQs > are rare and limited. Yes, the risk is that processing a fault synchronously will take too much time, leading to PRI queue overflow if the IOMMU keeps receiving page faults. That's why I opted for the workqueue initially, but it's definitely something we can tweak Thanks, Jean _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3231EC433C1 for ; Tue, 23 Mar 2021 10:53:05 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A25D9619BA for ; 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Tue, 23 Mar 2021 03:51:31 -0700 (PDT) Date: Tue, 23 Mar 2021 11:51:13 +0100 From: Jean-Philippe Brucker To: Lu Baolu Subject: Re: [PATCH v13 06/10] iommu: Add a page fault handler Message-ID: References: <20210302092644.2553014-1-jean-philippe@linaro.org> <20210302092644.2553014-7-jean-philippe@linaro.org> <15ff4704-0fbd-243f-8e49-a9523ae63ce6@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <15ff4704-0fbd-243f-8e49-a9523ae63ce6@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_105132_223184_F574D132 X-CRM114-Status: GOOD ( 11.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vivek.gautam@arm.com, guohanjun@huawei.com, will@kernel.org, lorenzo.pieralisi@arm.com, Ashok Raj , zhukeqian1@huawei.com, joro@8bytes.org, wangzhou1@hisilicon.com, linux-acpi@vger.kernel.org, zhangfei.gao@linaro.org, lenb@kernel.org, devicetree@vger.kernel.org, kevin.tian@intel.com, jacob.jun.pan@linux.intel.com, eric.auger@redhat.com, robh+dt@kernel.org, Jonathan.Cameron@huawei.com, linux-arm-kernel@lists.infradead.org, rjw@rjwysocki.net, shameerali.kolothum.thodi@huawei.com, iommu@lists.linux-foundation.org, sudeep.holla@arm.com, robin.murphy@arm.com, linux-accelerators@lists.ozlabs.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 03, 2021 at 01:27:34PM +0800, Lu Baolu wrote: > I have tested this framework with the Intel VT-d implementation. It > works as expected. Hence, > > Reviewed-by: Lu Baolu > Tested-by: Lu Baolu Thanks! > One possible future optimization is that we could allow the system > administrators to choose between handle PRQs in a workqueue or handle > them synchronously. One research discovered that most of the software > latency of handling a single page fault exists in the schedule part. > Hence, synchronous processing will get shorter software latency if PRQs > are rare and limited. Yes, the risk is that processing a fault synchronously will take too much time, leading to PRI queue overflow if the IOMMU keeps receiving page faults. That's why I opted for the workqueue initially, but it's definitely something we can tweak Thanks, Jean _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel