From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8831C433EB for ; Wed, 24 Mar 2021 12:40:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C69B661A0A for ; Wed, 24 Mar 2021 12:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234365AbhCXMjg (ORCPT ); Wed, 24 Mar 2021 08:39:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233111AbhCXMjU (ORCPT ); Wed, 24 Mar 2021 08:39:20 -0400 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C282C061763 for ; Wed, 24 Mar 2021 05:39:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=RrFr490dFRvD+R99oCaLdve7Nm3IkFIKrRyx/bsnPjw=; b=pCjx6OdE08VvbOSiDs5kXJYRfY lb6q5yV7oK21uCsJurgbts409+Y33BBPfIzSDl0cPL44qmR68W42PFq2xBQ0qGwVBugETmOVyaeot w1eswJnqfkAWVwstGiKCTAVFlNDVrkleJvnT+XxAU5SsNRpEGhEzIIQ7A4599wb8UzDRMpkgdU1IG AvWhv6UX1oD5IfuJZcBJk8R6ygN/zKr6YrqUgE+Uulzlozczzma83KFb7/s7Vi/mO81BfGLItSqux DI9uia8RCVxcbJr4sI09MAhA8ZTK1v/saDTRqlhCiK/sSHYl67RXk3MXvixORZZXJ+bQBVH1AedNa 67chedKA==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.94 #2 (Red Hat Linux)) id 1lP2lY-00BLAE-Vp; Wed, 24 Mar 2021 12:37:45 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 60B6B301A7A; Wed, 24 Mar 2021 13:37:40 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 4473E2BF5B73E; Wed, 24 Mar 2021 13:37:40 +0100 (CET) Date: Wed, 24 Mar 2021 13:37:40 +0100 From: Peter Zijlstra To: Anup Patel Cc: Guo Ren , linux-riscv , "linux-kernel@vger.kernel.org List" , Guo Ren , Catalin Marinas , Will Deacon , Palmer Dabbelt , Arnd Bergmann Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation Message-ID: References: <1616580892-80815-1-git-send-email-guoren@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote: > On Wed, Mar 24, 2021 at 3:45 PM wrote: > > > > From: Guo Ren > > > > This patch introduces a ticket lock implementation for riscv, along the > > same lines as the implementation for arch/arm & arch/csky. > > > > Signed-off-by: Guo Ren > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Peter Zijlstra > > Cc: Palmer Dabbelt > > Cc: Anup Patel > > Cc: Arnd Bergmann > > --- > > arch/riscv/Kconfig | 1 + > > arch/riscv/include/asm/Kbuild | 1 + > > arch/riscv/include/asm/spinlock.h | 158 ++++++++++++-------------------- > > arch/riscv/include/asm/spinlock_types.h | 19 ++-- > > NACK from myside. > > Linux ARM64 has moved away from ticket spinlock to qspinlock. > > We should directly go for qspinlock. I think it is a sensible intermediate step, even if you want to go qspinlock. Ticket locks are more or less trivial and get you fairness and all that goodness without the mind bending complexity of qspinlock. Once you have the ticket lock implementation solid (and qrwlock) and everything, *then* start to carefully look at qspinlock. Now, arguably arm64 did the heavy lifting of making qspinlock good on weak architectures, but if you want to do it right, you still have to analyze the whole thing for your own architecture. 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Wed, 24 Mar 2021 12:37:45 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 60B6B301A7A; Wed, 24 Mar 2021 13:37:40 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 4473E2BF5B73E; Wed, 24 Mar 2021 13:37:40 +0100 (CET) Date: Wed, 24 Mar 2021 13:37:40 +0100 From: Peter Zijlstra To: Anup Patel Cc: Guo Ren , linux-riscv , "linux-kernel@vger.kernel.org List" , Guo Ren , Catalin Marinas , Will Deacon , Palmer Dabbelt , Arnd Bergmann Subject: Re: [PATCH] riscv: locks: introduce ticket-based spinlock implementation Message-ID: References: <1616580892-80815-1-git-send-email-guoren@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Mar 24, 2021 at 05:58:58PM +0530, Anup Patel wrote: > On Wed, Mar 24, 2021 at 3:45 PM wrote: > > > > From: Guo Ren > > > > This patch introduces a ticket lock implementation for riscv, along the > > same lines as the implementation for arch/arm & arch/csky. > > > > Signed-off-by: Guo Ren > > Cc: Catalin Marinas > > Cc: Will Deacon > > Cc: Peter Zijlstra > > Cc: Palmer Dabbelt > > Cc: Anup Patel > > Cc: Arnd Bergmann > > --- > > arch/riscv/Kconfig | 1 + > > arch/riscv/include/asm/Kbuild | 1 + > > arch/riscv/include/asm/spinlock.h | 158 ++++++++++++-------------------- > > arch/riscv/include/asm/spinlock_types.h | 19 ++-- > > NACK from myside. > > Linux ARM64 has moved away from ticket spinlock to qspinlock. > > We should directly go for qspinlock. I think it is a sensible intermediate step, even if you want to go qspinlock. Ticket locks are more or less trivial and get you fairness and all that goodness without the mind bending complexity of qspinlock. Once you have the ticket lock implementation solid (and qrwlock) and everything, *then* start to carefully look at qspinlock. Now, arguably arm64 did the heavy lifting of making qspinlock good on weak architectures, but if you want to do it right, you still have to analyze the whole thing for your own architecture. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv