From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF727C433DB for ; Tue, 30 Mar 2021 03:23:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C8DCE619B6 for ; Tue, 30 Mar 2021 03:23:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231138AbhC3DXF (ORCPT ); Mon, 29 Mar 2021 23:23:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230328AbhC3DWv (ORCPT ); Mon, 29 Mar 2021 23:22:51 -0400 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBB0BC061765 for ; Mon, 29 Mar 2021 20:22:50 -0700 (PDT) Received: by mail-ot1-x32a.google.com with SMTP id y19-20020a0568301d93b02901b9f88a238eso14280659oti.11 for ; Mon, 29 Mar 2021 20:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=7t41cKlUPf2SnzIKDlby3FdcAtybZ6gP9vRyzm3tlpw=; b=TJNV3MVCQiasUwqdWIivjPmtxOlTOM1JFzmuOpR9nVs/xhurYQoXWzFj6vka6gfYKh M5YUGkd78B11wr1AdEIa9Qcc6G/+eyhgbltQO7vqHBoq42lkywNNLVeZBhYv6gS8k9Uy zApFG9rXYZ+cdBMyjDherT3Gnk2sZ7J32aONf0JqZFLjRj9X5brQ8V1+O5LGj6UYoa8x 5BYnrnfuIIScVKQ03JGW/yn6CMtjUCj6IkK/gfMntf+qRiyX3AK98tu/oYIdKw/IQLlo N6s3NJciHIcZcql/q6sYzASzKajau88T+2BRMKyuyy4NsZLbxcGECElNmCFy77c4+ndD S+Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=7t41cKlUPf2SnzIKDlby3FdcAtybZ6gP9vRyzm3tlpw=; b=UjBRsZY32p2EcGeNJVKvgZPOaedIf/mOFzDv8vru4gJf/a/ldQLodNVTbOP7MZFr3X JXts42tYze8Ym4QPiS7KdXBnojK3IeaKef3mdt2Or4fAKKBFubWEkQwp4uqHDJ2Y7/yl ayINcBs4rMGSjzQnZatoiIVLmplDptZtoFXb3svx1Q+AaVdkhUUDSAgajb8FLK0tdT0Q tZtd0LQWYfoWbL1XA/PYFUvMaP4UBGFCMpSqKUr2PZdBOn2Yqb/oNbFEkFYfqgW/Qnkp JasERu9G+R9v8rVIkldhrDziVMcTn111i32uYubMwfU3GkA1W6mIQsgXv3wKtwKRidn2 MnBQ== X-Gm-Message-State: AOAM5338L4lkvztFwbaUAomx4rbdFigkcX71nB0ND9bYJvANZzXkm+Tl hTZm0/IhX+BKRQihki4h4F6/vQ== X-Google-Smtp-Source: ABdhPJz07cbagzaVzHToP1yWalnf9L0GdocLLOt77CGY/q0IwhHE08v6oRtmLrtY0x/kftQXiO+LgQ== X-Received: by 2002:a05:6830:57:: with SMTP id d23mr24601867otp.44.1617074570171; Mon, 29 Mar 2021 20:22:50 -0700 (PDT) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id r20sm4954787otd.26.2021.03.29.20.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 20:22:49 -0700 (PDT) Date: Mon, 29 Mar 2021 22:22:47 -0500 From: Bjorn Andersson To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , Jordan Crouse , Robin Murphy , Will Deacon , Rob Herring , Joerg Roedel , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c. Message-ID: References: <20210326231303.3071950-1-eric@anholt.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210326231303.3071950-1-eric@anholt.net> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote: > db820c wants to use the qcom smmu path to get HUPCF set (which keeps > the GPU from wedging and then sometimes wedging the kernel after a > page fault), but it doesn't have separate pagetables support yet in > drm/msm so we can't go all the way to the TTBR1 path. > > Signed-off-by: Eric Anholt Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > > We've been seeing a flaky test per day or so in Mesa CI where the > kernel gets wedged after an iommu fault turns into CP errors. With > this patch, the CI isn't throwing the string of CP errors on the > faults in any of the ~10 jobs I've run so far. > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bcda17012aee..51f22193e456 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -130,6 +130,16 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma > return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > } > > +static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) > + return false; > + > + return true; > +} > + > static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > { > @@ -144,7 +154,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > * be AARCH64 stage 1 but double check because the arm-smmu code assumes > * that is the case when the TTBR1 quirk is enabled > */ > - if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && > + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > -- > 2.31.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC595C433DB for ; Tue, 30 Mar 2021 03:33:15 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55532617C9 for ; Tue, 30 Mar 2021 03:33:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 55532617C9 Authentication-Results: mail.kernel.org; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id r20sm4954787otd.26.2021.03.29.20.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 20:22:49 -0700 (PDT) Date: Mon, 29 Mar 2021 22:22:47 -0500 From: Bjorn Andersson To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , Jordan Crouse , Robin Murphy , Will Deacon , Rob Herring , Joerg Roedel , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c. Message-ID: References: <20210326231303.3071950-1-eric@anholt.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210326231303.3071950-1-eric@anholt.net> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210330_042252_069088_2D52E9D6 X-CRM114-Status: GOOD ( 25.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote: > db820c wants to use the qcom smmu path to get HUPCF set (which keeps > the GPU from wedging and then sometimes wedging the kernel after a > page fault), but it doesn't have separate pagetables support yet in > drm/msm so we can't go all the way to the TTBR1 path. > > Signed-off-by: Eric Anholt Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > > We've been seeing a flaky test per day or so in Mesa CI where the > kernel gets wedged after an iommu fault turns into CP errors. With > this patch, the CI isn't throwing the string of CP errors on the > faults in any of the ~10 jobs I've run so far. > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bcda17012aee..51f22193e456 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -130,6 +130,16 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma > return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > } > > +static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) > + return false; > + > + return true; > +} > + > static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > { > @@ -144,7 +154,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > * be AARCH64 stage 1 but double check because the arm-smmu code assumes > * that is the case when the TTBR1 quirk is enabled > */ > - if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && > + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > -- > 2.31.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69476C433DB for ; Tue, 30 Mar 2021 03:22:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1EE3A619B6 for ; Tue, 30 Mar 2021 03:22:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1EE3A619B6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D6AF89DDF; Tue, 30 Mar 2021 03:22:52 +0000 (UTC) Received: from mail-ot1-x330.google.com (mail-ot1-x330.google.com [IPv6:2607:f8b0:4864:20::330]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5DFA89DDF for ; Tue, 30 Mar 2021 03:22:50 +0000 (UTC) Received: by mail-ot1-x330.google.com with SMTP id k14-20020a9d7dce0000b02901b866632f29so14343037otn.1 for ; Mon, 29 Mar 2021 20:22:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=7t41cKlUPf2SnzIKDlby3FdcAtybZ6gP9vRyzm3tlpw=; b=TJNV3MVCQiasUwqdWIivjPmtxOlTOM1JFzmuOpR9nVs/xhurYQoXWzFj6vka6gfYKh M5YUGkd78B11wr1AdEIa9Qcc6G/+eyhgbltQO7vqHBoq42lkywNNLVeZBhYv6gS8k9Uy zApFG9rXYZ+cdBMyjDherT3Gnk2sZ7J32aONf0JqZFLjRj9X5brQ8V1+O5LGj6UYoa8x 5BYnrnfuIIScVKQ03JGW/yn6CMtjUCj6IkK/gfMntf+qRiyX3AK98tu/oYIdKw/IQLlo N6s3NJciHIcZcql/q6sYzASzKajau88T+2BRMKyuyy4NsZLbxcGECElNmCFy77c4+ndD S+Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=7t41cKlUPf2SnzIKDlby3FdcAtybZ6gP9vRyzm3tlpw=; b=O8/GiS2PBZaRH5HbdoVnapjKhqjGKfHAe26nU6J4wk3t5hpl+AGSsdSqXQEOAxEJ+I 9MBPA9GVF1Sw7CjfGBg0O5J3e46lxxVsr+o66RpCwHvm5mOMkaMPuyXp1MWwBdB7DPq/ Av+4b5PFkW2izvOVUTZAMNrMUjf76NozjC0X7B5QYrfJeWGjRjre/9uwMBLauJJjufLC /eTg35MVmTW8zCu3U2dTU1Yw8sjnanBkHmodMvhqktLohLuRLPJ75r05u6IyQclsegm2 Oj/64MVPJSSBkWQSjmmlmdmUJ7HKZSyo3TyMJICFWu28IpMUQul6DsOOqoF5LeKUiwbE Z10Q== X-Gm-Message-State: AOAM532kMy061XqiFgRp26YoI92tFlLc/T/yAvmOoYW4WexXZ9xs4KaT XSW7MKlnUtXQUmHdss/Az5qFYg== X-Google-Smtp-Source: ABdhPJz07cbagzaVzHToP1yWalnf9L0GdocLLOt77CGY/q0IwhHE08v6oRtmLrtY0x/kftQXiO+LgQ== X-Received: by 2002:a05:6830:57:: with SMTP id d23mr24601867otp.44.1617074570171; Mon, 29 Mar 2021 20:22:50 -0700 (PDT) Received: from builder.lan (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id r20sm4954787otd.26.2021.03.29.20.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 20:22:49 -0700 (PDT) Date: Mon, 29 Mar 2021 22:22:47 -0500 From: Bjorn Andersson To: Eric Anholt Subject: Re: [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c. Message-ID: References: <20210326231303.3071950-1-eric@anholt.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210326231303.3071950-1-eric@anholt.net> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: freedreno@lists.freedesktop.org, Will Deacon , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Joerg Roedel , Jordan Crouse , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Herring , Sean Paul , linux-arm-kernel@lists.infradead.org, Robin Murphy Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote: > db820c wants to use the qcom smmu path to get HUPCF set (which keeps > the GPU from wedging and then sometimes wedging the kernel after a > page fault), but it doesn't have separate pagetables support yet in > drm/msm so we can't go all the way to the TTBR1 path. > > Signed-off-by: Eric Anholt Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > > We've been seeing a flaky test per day or so in Mesa CI where the > kernel gets wedged after an iommu fault turns into CP errors. With > this patch, the CI isn't throwing the string of CP errors on the > faults in any of the ~10 jobs I've run so far. > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bcda17012aee..51f22193e456 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -130,6 +130,16 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma > return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > } > > +static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) > + return false; > + > + return true; > +} > + > static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > { > @@ -144,7 +154,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > * be AARCH64 stage 1 but double check because the arm-smmu code assumes > * that is the case when the TTBR1 quirk is enabled > */ > - if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && > + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > -- > 2.31.0 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel