From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DA65C43460 for ; Thu, 15 Apr 2021 07:53:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D235D61249 for ; Thu, 15 Apr 2021 07:53:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231389AbhDOHyF (ORCPT ); Thu, 15 Apr 2021 03:54:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:51928 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231215AbhDOHyE (ORCPT ); Thu, 15 Apr 2021 03:54:04 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 182A560FF1; Thu, 15 Apr 2021 07:53:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1618473220; bh=wBbsq3BHxR0U3Gvztafs7IZfL5R/LWbYaqcp+rGIddc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=malk0Q1T6WsJdGmTQ+Gw5zh+K+/ylDTnbDHWrX69H83FHQ++xUhrVxEw5CPSnRnv7 v8cpu8aRYgth14o97xu1XXnO8qs1mtxGysWR4JKJONnLDnBZLnVPCTphSMCZUx2ndE tlPlYVlT4KTD8Yt+W+Cr8Usl5v8wnzEmieVRpcwY= Date: Thu, 15 Apr 2021 09:53:38 +0200 From: Greg Kroah-Hartman To: Thinh Nguyen Cc: Felipe Balbi , "linux-usb@vger.kernel.org" , Roger Quadros , John Youn , "stable@vger.kernel.org" , Andy Shevchenko , John Stultz , Wesley Cheng , Ferry Toth , Yu Chen Subject: Re: [PATCH] usb: dwc3: core: Do core softreset when switch mode Message-ID: References: <96c64e6a788552371081f37f544041b7ee046ef5.1618452732.git.Thinh.Nguyen@synopsys.com> <87sg3snk1l.fsf@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org On Thu, Apr 15, 2021 at 07:10:34AM +0000, Thinh Nguyen wrote: > Felipe Balbi wrote: > > > > Hi, > > > > Thinh Nguyen writes: > >> From: Yu Chen > >> From: John Stultz > >> > >> According to the programming guide, to switch mode for DRD controller, > >> the driver needs to do the following. > >> > >> To switch from device to host: > >> 1. Reset controller with GCTL.CoreSoftReset > >> 2. Set GCTL.PrtCapDir(host mode) > >> 3. Reset the host with USBCMD.HCRESET > >> 4. Then follow up with the initializing host registers sequence > >> > >> To switch from host to device: > >> 1. Reset controller with GCTL.CoreSoftReset > >> 2. Set GCTL.PrtCapDir(device mode) > >> 3. Reset the device with DCTL.CSftRst > >> 4. Then follow up with the initializing registers sequence > >> > >> Currently we're missing step 1) to do GCTL.CoreSoftReset and step 3) of > > > > we're not really missing, it was a deliberate choice :-) The only reason > > why we need the soft reset is because host and gadget registers map to > > the same physical space within dwc3 core. If we cache and restore the > > affected registers, we're good ;-) > > It's part of the programming model. I've already discussed with internal > RTL designers. This is needed, and I've provided the discussion we had > prior also. We have several different devices in the wild that need > this. What is the concern? > > > > > IMHO, that's a better compromise than doing a full soft reset. > > > >> @@ -40,6 +41,8 @@ > >> > >> #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ > >> > >> +static DEFINE_MUTEX(mode_switch_lock); > > > > there are several platforms which more than one DWC3 instance. Sure this > > won't break on such systems? > > > > How? Am I missing something? Please let me know so I can make the change. All data needs to be per-device, not "global for the codebase" like the way you declared this lock. thanks, greg k-h