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[35.247.111.240]) by smtp.gmail.com with ESMTPSA id h18sm5059108pgj.51.2021.04.23.07.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Apr 2021 07:12:36 -0700 (PDT) Date: Fri, 23 Apr 2021 14:12:32 +0000 From: Sean Christopherson To: Paolo Bonzini Cc: Reiji Watanabe , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Lendacky Subject: Re: [PATCH v2] KVM: SVM: Delay restoration of host MSR_TSC_AUX until return to userspace Message-ID: References: <20210422001736.3255735-1-seanjc@google.com> <8cc2bb9a-167e-598c-6a9e-c23e943b1248@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8cc2bb9a-167e-598c-6a9e-c23e943b1248@redhat.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 23, 2021, Paolo Bonzini wrote: > On 22/04/21 22:12, Sean Christopherson wrote: > > case MSR_TSC_AUX: > > if (!boot_cpu_has(X86_FEATURE_RDTSCP)) > > return 1; > > > > if (!msr_info->host_initiated && > > !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) > > return 1; > > > > /* > > * TSC_AUX is usually changed only during boot and never read > > * directly. Intercept TSC_AUX instead of exposing it to the > > * guest via direct_access_msrs, and switch it via user return. > > */ > > preempt_disable(); > > r = kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull); > > preempt_enable(); > > if (r) > > return 1; > > > > /* > > * Bits 63:32 are dropped by AMD CPUs, but are reserved on > > * Intel CPUs. AMD's APM has incomplete and conflicting info > > * on the architectural behavior; emulate current hardware as > > * doing so ensures migrating from AMD to Intel won't explode. > > */ > > svm->tsc_aux = (u32)data; > > break; > > > > Ok, squashed in the following: Too fast! The below won't compile (s/msr_info/msr and 'r' needs to be defined), and the get_msr() path needs the guest_cpuid_has() check. I'll spin a v3. > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index 14ff7f0963e9..00e9680969a2 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -2875,16 +2875,28 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) > if (!boot_cpu_has(X86_FEATURE_RDTSCP)) > return 1; > + if (!msr_info->host_initiated && > + !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) > + return 1; > + > /* > * TSC_AUX is usually changed only during boot and never read > * directly. Intercept TSC_AUX instead of exposing it to the > * guest via direct_access_msrs, and switch it via user return. > */ > - svm->tsc_aux = data; > - > preempt_disable(); > - kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull); > + r = kvm_set_user_return_msr(TSC_AUX_URET_SLOT, data, -1ull); > preempt_enable(); > + if (r) > + return 1; > + > + /* > + * Bits 63:32 are dropped by AMD CPUs, but are reserved on > + * Intel CPUs. AMD's APM has incomplete and conflicting info > + * on the architectural behavior; emulate current hardware as > + * doing so ensures migrating from AMD to Intel won't explode. > + */ > + svm->tsc_aux = (u32)data; > break; > case MSR_IA32_DEBUGCTLMSR: > if (!boot_cpu_has(X86_FEATURE_LBRV)) { > > Paolo >