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[93.35.189.2]) by smtp.gmail.com with ESMTPSA id d18sm10236939edv.1.2021.04.24.14.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Apr 2021 14:20:20 -0700 (PDT) Date: Sat, 24 Apr 2021 23:18:20 +0200 From: Ansuel Smith To: Florian Fainelli Cc: Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/14] drivers: net: dsa: qca8k: apply switch revision fix Message-ID: References: <20210423014741.11858-1-ansuelsmth@gmail.com> <20210423014741.11858-12-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 22, 2021 at 07:02:37PM -0700, Florian Fainelli wrote: > > > On 4/22/2021 6:47 PM, Ansuel Smith wrote: > > qca8k require special debug value based on the switch revision. > > > > Signed-off-by: Ansuel Smith > > --- > > drivers/net/dsa/qca8k.c | 23 +++++++++++++++++++++-- > > 1 file changed, 21 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c > > index 193c269d8ed3..12d2c97d1417 100644 > > --- a/drivers/net/dsa/qca8k.c > > +++ b/drivers/net/dsa/qca8k.c > > @@ -909,7 +909,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, > > { > > const struct qca8k_match_data *data; > > struct qca8k_priv *priv = ds->priv; > > - u32 reg, val; > > + u32 phy, reg, val; > > > > /* get the switches ID from the compatible */ > > data = of_device_get_match_data(priv->dev); > > @@ -928,7 +928,26 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, > > case 3: > > case 4: > > case 5: > > - /* Internal PHY, nothing to do */ > > + /* Internal PHY, apply revision fixup */ > > + phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; > > + switch (priv->switch_revision) { > > + case 1: > > + /* For 100M waveform */ > > + qca8k_phy_dbg_write(priv, phy, 0, 0x02ea); > > + /* Turn on Gigabit clock */ > > + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x68a0); > > + break; > > + > > + case 2: > > + qca8k_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0); > > + fallthrough; > > + case 4: > > + qca8k_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f); > > + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x6860); > > + qca8k_phy_dbg_write(priv, phy, 0x5, 0x2c46); > > + qca8k_phy_dbg_write(priv, phy, 0x3c, 0x6000); > > + break; > > This would be better done with a PHY driver that is specific to the > integrated PHY found in these switches, it would provide a nice clean > layer and would allow you to expose additional features like cable > tests, PHY statistics/counters, etc. I'm starting to do some work with this and a problem arised. Since these value are based on the switch revision, how can I access these kind of data from the phy driver? It's allowed to declare a phy driver in the dsa directory? (The idea would be to create a qca8k dir with the dsa driver and the dedicated internal phy driver.) This would facilitate the use of normal qca8k_read/write (to access the switch revision from the phy driver) using common function? > -- > Florian