From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAE29C433ED for ; Sun, 25 Apr 2021 14:33:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9952661152 for ; Sun, 25 Apr 2021 14:33:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230346AbhDYOeX (ORCPT ); Sun, 25 Apr 2021 10:34:23 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:39878 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229906AbhDYOeV (ORCPT ); Sun, 25 Apr 2021 10:34:21 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lafpD-000zu0-0c; Sun, 25 Apr 2021 16:33:31 +0200 Date: Sun, 25 Apr 2021 16:33:30 +0200 From: Andrew Lunn To: Ansuel Smith Cc: DENG Qingfang , Florian Fainelli , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 11/14] drivers: net: dsa: qca8k: apply switch revision fix Message-ID: References: <20210423014741.11858-1-ansuelsmth@gmail.com> <20210423014741.11858-12-ansuelsmth@gmail.com> <20210425044554.194770-1-dqfext@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Apr 25, 2021 at 01:59:19PM +0200, Ansuel Smith wrote: > On Sun, Apr 25, 2021 at 12:45:54PM +0800, DENG Qingfang wrote: > > Hi Ansuel, > > > > On Sat, Apr 24, 2021 at 11:18:20PM +0200, Ansuel Smith wrote: > > > > > > I'm starting to do some work with this and a problem arised. Since these > > > value are based on the switch revision, how can I access these kind of > > > data from the phy driver? It's allowed to declare a phy driver in the > > > dsa directory? (The idea would be to create a qca8k dir with the dsa > > > driver and the dedicated internal phy driver.) This would facilitate the > > > use of normal qca8k_read/write (to access the switch revision from the > > > phy driver) using common function? > > > > In case of different switch revision, the PHY ID should also be different. > > I think you can reuse the current at803x.c PHY driver, as they seem to > > share similar registers. > > > > Is this really necessary? Every PHY has the same ID linked to the switch > id but the revision can change across the same switch id. Isn't the phy > dev flag enought to differiante one id from another? Just as general background information: A PHY ID generally consists of three parts. 1) OUI - Identifies the manufacture - 22 bits 2) device - Generally 6 bits 3) revision - Generally 4 bits The 22 bits of OUI is standardized. But the last 10 bits the vendor can use as they wish. But generally, this is how it is used. Loading the PHY driver is generally based on matching the OUI and device ID. The revision is ignored. But it is available to the driver if needed. It could be, the switch revision is also reflected in the PHY revision. Andrew