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[35.247.111.240]) by smtp.gmail.com with ESMTPSA id 184sm15445516pfv.38.2021.05.26.08.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 08:15:07 -0700 (PDT) Date: Wed, 26 May 2021 15:15:03 +0000 From: Sean Christopherson To: Reiji Watanabe Cc: Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 17/43] KVM: x86: Open code necessary bits of kvm_lapic_set_base() at vCPU RESET Message-ID: References: <20210424004645.3950558-1-seanjc@google.com> <20210424004645.3950558-18-seanjc@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 26, 2021, Reiji Watanabe wrote: > On Fri, Apr 23, 2021 at 5:51 PM Sean Christopherson wrote: > > > > Stuff vcpu->arch.apic_base and apic->base_address directly during APIC > > reset, as opposed to bouncing through kvm_set_apic_base() while fudging > > the ENABLE bit during creation to avoid the other, unwanted side effects. > > > > This is a step towards consolidating the APIC RESET logic across x86, > > VMX, and SVM. > > > > Signed-off-by: Sean Christopherson > > --- > > arch/x86/kvm/lapic.c | 15 ++++++--------- > > 1 file changed, 6 insertions(+), 9 deletions(-) > > > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > > index b088f6984b37..b1366df46d1d 100644 > > --- a/arch/x86/kvm/lapic.c > > +++ b/arch/x86/kvm/lapic.c > > @@ -2305,7 +2305,6 @@ EXPORT_SYMBOL_GPL(kvm_apic_update_apicv); > > void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) > > { > > struct kvm_lapic *apic = vcpu->arch.apic; > > - u64 msr_val; > > int i; > > > > if (!apic) > > @@ -2315,10 +2314,13 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) > > hrtimer_cancel(&apic->lapic_timer.timer); > > > > if (!init_event) { > > - msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE; > > + vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE | > > + MSR_IA32_APICBASE_ENABLE; > > if (kvm_vcpu_is_reset_bsp(vcpu)) > > - msr_val |= MSR_IA32_APICBASE_BSP; > > - kvm_lapic_set_base(vcpu, msr_val); > > + vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP; > > + > > + apic->base_address = MSR_IA32_APICBASE_ENABLE; > > I think you wanted to make the code above set apic->base_address > to APIC_DEFAULT_PHYS_BASE (not MSR_IA32_APICBASE_ENABLE). Indeed! It also means I need to double check that I'm testing a guest without x2apic enabled. Thanks much!