From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B08D570 for ; Fri, 21 May 2021 18:25:26 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id D3049613E2; Fri, 21 May 2021 18:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1621621526; bh=9AcZJfeo0xf1euRFblZG0MfqbBmLwbiLEIEackPiTqA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=0LBTP5aGzuiN5qYxA5cNt6W4SscUFYtUHumwamPn5Ztt1ht4YhL0u1ltJnjB1YUcx Omlw2tyXOaYoH+f7UwfsC2EQ2dUPcDcVkYUFJ3KfXUxzFp9WptKLX3fXamJ5dkGMuK +5FhSMdxVEDIsBv/267cHa1UzuZg2WeNhKH75vKI= Date: Fri, 21 May 2021 20:25:23 +0200 From: Greg KH To: Palmer Dabbelt Cc: pbonzini@redhat.com, anup@brainfault.org, Anup Patel , Paul Walmsley , aou@eecs.berkeley.edu, corbet@lwn.net, graf@amazon.com, Atish Patra , Alistair Francis , Damien Le Moal , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v18 00/18] KVM RISC-V Support Message-ID: References: X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, May 21, 2021 at 11:08:15AM -0700, Palmer Dabbelt wrote: > On Fri, 21 May 2021 10:47:51 PDT (-0700), Greg KH wrote: > > On Fri, May 21, 2021 at 07:21:12PM +0200, Paolo Bonzini wrote: > > > On 21/05/21 19:13, Palmer Dabbelt wrote: > > > > > > > > > > > > > I don't view this code as being in a state where it can be > > > > maintained, at least to the standards we generally set within the > > > > kernel. The ISA extension in question is still subject to change, it > > > > says so right at the top of the H extension > > > > > > > > {\bf Warning! This draft specification may change before being > > > > accepted as standard by the RISC-V Foundation.} > > > > > > To give a complete picture, the last three relevant changes have been in > > > August 2019, November 2019 and May 2020. It seems pretty frozen to me. > > > > > > In any case, I think it's clear from the experience with Android that > > > the acceptance policy cannot succeed. The only thing that such a policy > > > guarantees, is that vendors will use more out-of-tree code. Keeping a > > > fully-developed feature out-of-tree for years is not how Linux is run. > > > > > > > I'm not sure where exactly the line for real hardware is, but for > > > > something like this it would at least involve some chip that is > > > > widely availiable and needs the H extension to be useful > > > > > > Anup said that "quite a few people have already implemented RISC-V > > > H-extension in hardware as well and KVM RISC-V works on real HW as well". > > > Those people would benefit from having KVM in the Linus tree. > > > > Great, but is this really true? If so, what hardware has this? I have > > a new RISC-V device right here next to me, what would I need to do to > > see if this is supported in it or not? > > You can probe the misa register, it should have the H bit set if it supports > the H extension. To let everyone know, based on our private chat we had off-list, no, the device I have does not support this extension, so unless someone can point me at real hardware, I don't think this code needs to be considered for merging anywhere just yet. thanks, greg k-h From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B47DC4707C for ; Fri, 21 May 2021 18:25:54 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4A6B610A8 for ; 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Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lk9pu-00HLv4-TJ; Fri, 21 May 2021 18:25:28 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id D3049613E2; Fri, 21 May 2021 18:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1621621526; bh=9AcZJfeo0xf1euRFblZG0MfqbBmLwbiLEIEackPiTqA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=0LBTP5aGzuiN5qYxA5cNt6W4SscUFYtUHumwamPn5Ztt1ht4YhL0u1ltJnjB1YUcx Omlw2tyXOaYoH+f7UwfsC2EQ2dUPcDcVkYUFJ3KfXUxzFp9WptKLX3fXamJ5dkGMuK +5FhSMdxVEDIsBv/267cHa1UzuZg2WeNhKH75vKI= Date: Fri, 21 May 2021 20:25:23 +0200 From: Greg KH To: Palmer Dabbelt Cc: pbonzini@redhat.com, anup@brainfault.org, Anup Patel , Paul Walmsley , aou@eecs.berkeley.edu, corbet@lwn.net, graf@amazon.com, Atish Patra , Alistair Francis , Damien Le Moal , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v18 00/18] KVM RISC-V Support Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210521_112526_987083_468CA233 X-CRM114-Status: GOOD ( 30.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 21, 2021 at 11:08:15AM -0700, Palmer Dabbelt wrote: > On Fri, 21 May 2021 10:47:51 PDT (-0700), Greg KH wrote: > > On Fri, May 21, 2021 at 07:21:12PM +0200, Paolo Bonzini wrote: > > > On 21/05/21 19:13, Palmer Dabbelt wrote: > > > > > > > > > > > > > I don't view this code as being in a state where it can be > > > > maintained, at least to the standards we generally set within the > > > > kernel. The ISA extension in question is still subject to change, it > > > > says so right at the top of the H extension > > > > > > > > {\bf Warning! This draft specification may change before being > > > > accepted as standard by the RISC-V Foundation.} > > > > > > To give a complete picture, the last three relevant changes have been in > > > August 2019, November 2019 and May 2020. It seems pretty frozen to me. > > > > > > In any case, I think it's clear from the experience with Android that > > > the acceptance policy cannot succeed. The only thing that such a policy > > > guarantees, is that vendors will use more out-of-tree code. Keeping a > > > fully-developed feature out-of-tree for years is not how Linux is run. > > > > > > > I'm not sure where exactly the line for real hardware is, but for > > > > something like this it would at least involve some chip that is > > > > widely availiable and needs the H extension to be useful > > > > > > Anup said that "quite a few people have already implemented RISC-V > > > H-extension in hardware as well and KVM RISC-V works on real HW as well". > > > Those people would benefit from having KVM in the Linus tree. > > > > Great, but is this really true? If so, what hardware has this? I have > > a new RISC-V device right here next to me, what would I need to do to > > see if this is supported in it or not? > > You can probe the misa register, it should have the H bit set if it supports > the H extension. To let everyone know, based on our private chat we had off-list, no, the device I have does not support this extension, so unless someone can point me at real hardware, I don't think this code needs to be considered for merging anywhere just yet. thanks, greg k-h _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv