From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C71E8C47082 for ; Tue, 8 Jun 2021 20:47:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4A6B61185 for ; Tue, 8 Jun 2021 20:47:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230246AbhFHUtO (ORCPT ); Tue, 8 Jun 2021 16:49:14 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:53024 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230214AbhFHUtN (ORCPT ); Tue, 8 Jun 2021 16:49:13 -0400 Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7FD3C3E6; Tue, 8 Jun 2021 22:47:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1623185238; bh=nL94lwxiZDx7hO51vSX7RllgqbEzWiXMfFLGeKO44RU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=LqehrYH7+bNvxnCFiQRU5fOnAU8KAbzQFhAmjEpkGwrRsydbIiNAxFHhFDXenTXD3 n6J0D/aEgZ2SJklelIKb8IWd1J7FBRkKGzPRnTIf89afSIo+VcOQTIa3IXSSJfbWQK J1f7W0/ODl1SjdZjDcwJnS1XftTAUlSoAnj1gfM0= Date: Tue, 8 Jun 2021 23:47:02 +0300 From: Laurent Pinchart To: Jonathan Marek Cc: freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Vinod Koul , Anurag Kumar Vulisha , Swapnil Jakhade , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Subject: Re: [PATCH v3 2/3] dt-bindings: msm: dsi: document phy-type property for 7nm dsi phy Message-ID: References: <20210608195342.18269-1-jonathan@marek.ca> <20210608195342.18269-3-jonathan@marek.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210608195342.18269-3-jonathan@marek.ca> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Jonathan, Thank you for the patch. On Tue, Jun 08, 2021 at 03:53:28PM -0400, Jonathan Marek wrote: > Document a new phy-type property which will be used to determine whether > the phy should operate in D-PHY or C-PHY mode. > > Signed-off-by: Jonathan Marek > --- > .../devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 4 ++++ > include/dt-bindings/phy/phy.h | 2 ++ > 2 files changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml > index bf16b1c65e10..d447b517ea19 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml > @@ -34,6 +34,10 @@ properties: > description: | > Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150) > > + phy-type: > + description: | > + D-PHY (default) or C-PHY mode: PHY_TYPE_DSI_DPHY or PHY_TYPE_DSI_CPHY > + > required: > - compatible > - reg > diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h > index 887a31b250a8..b978dac16bb8 100644 > --- a/include/dt-bindings/phy/phy.h > +++ b/include/dt-bindings/phy/phy.h > @@ -20,5 +20,7 @@ > #define PHY_TYPE_XPCS 7 > #define PHY_TYPE_SGMII 8 > #define PHY_TYPE_QSGMII 9 > +#define PHY_TYPE_DSI_DPHY 10 > +#define PHY_TYPE_DSI_CPHY 11 The MIPI D-PHY and C-PHY apply to both DSI and CSI. I'd name this PHY_TYPE_DPHY and PHY_TYPE_CPHY, or possibly, PHY_TYPE_MIPI_DPHY and PHY_TYPE_MIPI_CPHY, without a DSI prefix. With this addressed and the DT bindings updated accordingly, Reviewed-by: Laurent Pinchart (You may be asked to split this in two patches though, not sure) > #endif /* _DT_BINDINGS_PHY */ -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0CB8C48BCD for ; Tue, 8 Jun 2021 20:47:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 055F361185 for ; Tue, 8 Jun 2021 20:47:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 055F361185 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7289D6E20F; Tue, 8 Jun 2021 20:47:22 +0000 (UTC) Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id B83DE6E1CF for ; Tue, 8 Jun 2021 20:47:20 +0000 (UTC) Received: from pendragon.ideasonboard.com (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7FD3C3E6; Tue, 8 Jun 2021 22:47:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1623185238; bh=nL94lwxiZDx7hO51vSX7RllgqbEzWiXMfFLGeKO44RU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=LqehrYH7+bNvxnCFiQRU5fOnAU8KAbzQFhAmjEpkGwrRsydbIiNAxFHhFDXenTXD3 n6J0D/aEgZ2SJklelIKb8IWd1J7FBRkKGzPRnTIf89afSIo+VcOQTIa3IXSSJfbWQK J1f7W0/ODl1SjdZjDcwJnS1XftTAUlSoAnj1gfM0= Date: Tue, 8 Jun 2021 23:47:02 +0300 From: Laurent Pinchart To: Jonathan Marek Subject: Re: [PATCH v3 2/3] dt-bindings: msm: dsi: document phy-type property for 7nm dsi phy Message-ID: References: <20210608195342.18269-1-jonathan@marek.ca> <20210608195342.18269-3-jonathan@marek.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210608195342.18269-3-jonathan@marek.ca> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Anurag Kumar Vulisha , David Airlie , freedreno@lists.freedesktop.org, "open list:DRM DRIVER FOR MSM ADRENO GPU" , Vinod Koul , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , Rob Herring , Swapnil Jakhade , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Jonathan, Thank you for the patch. On Tue, Jun 08, 2021 at 03:53:28PM -0400, Jonathan Marek wrote: > Document a new phy-type property which will be used to determine whether > the phy should operate in D-PHY or C-PHY mode. > > Signed-off-by: Jonathan Marek > --- > .../devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 4 ++++ > include/dt-bindings/phy/phy.h | 2 ++ > 2 files changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml > index bf16b1c65e10..d447b517ea19 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml > +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml > @@ -34,6 +34,10 @@ properties: > description: | > Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150) > > + phy-type: > + description: | > + D-PHY (default) or C-PHY mode: PHY_TYPE_DSI_DPHY or PHY_TYPE_DSI_CPHY > + > required: > - compatible > - reg > diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h > index 887a31b250a8..b978dac16bb8 100644 > --- a/include/dt-bindings/phy/phy.h > +++ b/include/dt-bindings/phy/phy.h > @@ -20,5 +20,7 @@ > #define PHY_TYPE_XPCS 7 > #define PHY_TYPE_SGMII 8 > #define PHY_TYPE_QSGMII 9 > +#define PHY_TYPE_DSI_DPHY 10 > +#define PHY_TYPE_DSI_CPHY 11 The MIPI D-PHY and C-PHY apply to both DSI and CSI. I'd name this PHY_TYPE_DPHY and PHY_TYPE_CPHY, or possibly, PHY_TYPE_MIPI_DPHY and PHY_TYPE_MIPI_CPHY, without a DSI prefix. With this addressed and the DT bindings updated accordingly, Reviewed-by: Laurent Pinchart (You may be asked to split this in two patches though, not sure) > #endif /* _DT_BINDINGS_PHY */ -- Regards, Laurent Pinchart