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Tue, 01 Jun 2021 07:25:59 -0700 (PDT) Date: Tue, 1 Jun 2021 16:25:57 +0200 From: Daniel Vetter To: Tvrtko Ursulin Subject: Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING Message-ID: References: <20210525135508.244659-1-tejaskumarx.surendrakumar.upadhyay@intel.com> <20210525135508.244659-2-tejaskumarx.surendrakumar.upadhyay@intel.com> <8cf2c5f4-87a3-ce6b-150c-65fa054586a4@linux.intel.com> <59d2eee9-35c1-01fc-c226-50ad98aadb99@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Operating-System: Linux phenom 5.10.32scarlett+ X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Tejas Upadhyay , DRI Development , mahesh.meena@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Jun 01, 2021 at 11:09:47AM +0100, Tvrtko Ursulin wrote: > > On 27/05/2021 11:27, Daniel Vetter wrote: > > On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote: > > > > > > On 27/05/2021 11:13, Daniel Vetter wrote: > > > > On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > On 25/05/2021 15:47, Daniel Vetter wrote: > > > > > > On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > + dri-devel as per process > > > > > > > > > > > > > > On 25/05/2021 14:55, Tejas Upadhyay wrote: > > > > > > > > v2: Only declare timeslicing if we can safely preempt userspace. > > > > > > > > > > > > > > Commit message got butchered up somehow so you'll need to fix that at some > > > > > > > point. > > > > > > > > > > > > > > Regards, > > > > > > > > > > > > > > Tvrtko > > > > > > > > > > > > > > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > > > > > > > > Signed-off-by: Chris Wilson > > > > > > > > Cc: Tvrtko Ursulin > > > > > > > > Reviewed-by: Tvrtko Ursulin > > > > > > > > --- > > > > > > > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + > > > > > > > > include/uapi/drm/i915_drm.h | 1 + > > > > > > > > 2 files changed, 2 insertions(+) > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > index 3cca7ea2d6ea..12d165566ed2 100644 > > > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) > > > > > > > > MAP(HAS_PREEMPTION, PREEMPTION), > > > > > > > > MAP(HAS_SEMAPHORES, SEMAPHORES), > > > > > > > > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), > > > > > > > > + MAP(TIMESLICE_BIT, TIMESLICING), > > > > > > > > #undef MAP > > > > > > > > }; > > > > > > > > struct intel_engine_cs *engine; > > > > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > > > > > > > index c2c7759b7d2e..af2212d6113c 100644 > > > > > > > > --- a/include/uapi/drm/i915_drm.h > > > > > > > > +++ b/include/uapi/drm/i915_drm.h > > > > > > > > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { > > > > > > > > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) > > > > > > > > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) > > > > > > > > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) > > > > > > > > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) > > > > > > > > > > > > Since this is uapi I think we should at least have some nice kerneldoc > > > > > > that explains what exactly this is, what for (link to userspace) and all > > > > > > that. Ideally also minimally filing in the gaps in our uapi docs for stuff > > > > > > this references. > > > > > > > > > > IIUC there is no userspace apart from IGT needing it not to fail scheduling > > > > > tests on ADL. > > > > > > > > > > Current tests use "has preemption + has semaphores" as a proxy to answer the > > > > > "does the kernel support timeslicing" question. This stops working with the > > > > > Guc backend because GuC decided not to support semaphores (for reasons yet > > > > > unknown, see other thread), so explicit "has timeslicing" flag is needed in > > > > > order for tests to know that GuC is supposed to support timeslicing, even if > > > > > it doesn't use semaphores for inter-ring synchronisation. > > > > > > > > Since this if for igt only: Cant we do just extend the check in igt with > > > > an || GEN >= 12? I really hope that our future hw will continue to support > > > > timeslicing ... > > > > > > Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: > > > > > > has_timeslicing = > > > (has_preemption && has_semaphores) || uses_guc_submission; > > > > That works too. Otoh what exactly is the "uses guc submission" flag and > > why do we have that? I've seen media use it as a stand-in for "does the > > kernel want bonded or parallel ctx?". Maybe another thing to check. > > > > Another option, if you really think the feature flag is the best approach > > (because future hw will drop timeslicing for some reason), then debugfs is > > the place of igt-only api. > > Maybe check and potentially remove all I915_SCHEDULER_CAP_.. flags. It could > be another easy pickings with a lot of IGT work type endeavour. Yeah there's a lot unfortunately. I'll make a note internally that we need to look at this again maybe next year, but for now we're going to only concentrate on stuff that has actual architecture/design impact. In the grand scheme of things exporting a bunch of flags for igt in the uapi is mostly harmless. There's much bigger fish to fry were we allow igt to make changes to objects that should be all immutable. Those need to be worked out first. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB7D6C47080 for ; Tue, 1 Jun 2021 14:26:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6AC2E613A9 for ; Tue, 1 Jun 2021 14:26:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6AC2E613A9 Authentication-Results: mail.kernel.org; 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Tue, 01 Jun 2021 07:25:59 -0700 (PDT) Date: Tue, 1 Jun 2021 16:25:57 +0200 From: Daniel Vetter To: Tvrtko Ursulin Message-ID: References: <20210525135508.244659-1-tejaskumarx.surendrakumar.upadhyay@intel.com> <20210525135508.244659-2-tejaskumarx.surendrakumar.upadhyay@intel.com> <8cf2c5f4-87a3-ce6b-150c-65fa054586a4@linux.intel.com> <59d2eee9-35c1-01fc-c226-50ad98aadb99@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Operating-System: Linux phenom 5.10.32scarlett+ Subject: Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, DRI Development , mahesh.meena@intel.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, Jun 01, 2021 at 11:09:47AM +0100, Tvrtko Ursulin wrote: > > On 27/05/2021 11:27, Daniel Vetter wrote: > > On Thu, May 27, 2021 at 11:22:16AM +0100, Tvrtko Ursulin wrote: > > > > > > On 27/05/2021 11:13, Daniel Vetter wrote: > > > > On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > On 25/05/2021 15:47, Daniel Vetter wrote: > > > > > > On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > + dri-devel as per process > > > > > > > > > > > > > > On 25/05/2021 14:55, Tejas Upadhyay wrote: > > > > > > > > v2: Only declare timeslicing if we can safely preempt userspace. > > > > > > > > > > > > > > Commit message got butchered up somehow so you'll need to fix that at some > > > > > > > point. > > > > > > > > > > > > > > Regards, > > > > > > > > > > > > > > Tvrtko > > > > > > > > > > > > > > > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") > > > > > > > > Signed-off-by: Chris Wilson > > > > > > > > Cc: Tvrtko Ursulin > > > > > > > > Reviewed-by: Tvrtko Ursulin > > > > > > > > --- > > > > > > > > drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + > > > > > > > > include/uapi/drm/i915_drm.h | 1 + > > > > > > > > 2 files changed, 2 insertions(+) > > > > > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > index 3cca7ea2d6ea..12d165566ed2 100644 > > > > > > > > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c > > > > > > > > @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) > > > > > > > > MAP(HAS_PREEMPTION, PREEMPTION), > > > > > > > > MAP(HAS_SEMAPHORES, SEMAPHORES), > > > > > > > > MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), > > > > > > > > + MAP(TIMESLICE_BIT, TIMESLICING), > > > > > > > > #undef MAP > > > > > > > > }; > > > > > > > > struct intel_engine_cs *engine; > > > > > > > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > > > > > > > index c2c7759b7d2e..af2212d6113c 100644 > > > > > > > > --- a/include/uapi/drm/i915_drm.h > > > > > > > > +++ b/include/uapi/drm/i915_drm.h > > > > > > > > @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { > > > > > > > > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) > > > > > > > > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) > > > > > > > > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) > > > > > > > > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) > > > > > > > > > > > > Since this is uapi I think we should at least have some nice kerneldoc > > > > > > that explains what exactly this is, what for (link to userspace) and all > > > > > > that. Ideally also minimally filing in the gaps in our uapi docs for stuff > > > > > > this references. > > > > > > > > > > IIUC there is no userspace apart from IGT needing it not to fail scheduling > > > > > tests on ADL. > > > > > > > > > > Current tests use "has preemption + has semaphores" as a proxy to answer the > > > > > "does the kernel support timeslicing" question. This stops working with the > > > > > Guc backend because GuC decided not to support semaphores (for reasons yet > > > > > unknown, see other thread), so explicit "has timeslicing" flag is needed in > > > > > order for tests to know that GuC is supposed to support timeslicing, even if > > > > > it doesn't use semaphores for inter-ring synchronisation. > > > > > > > > Since this if for igt only: Cant we do just extend the check in igt with > > > > an || GEN >= 12? I really hope that our future hw will continue to support > > > > timeslicing ... > > > > > > Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: > > > > > > has_timeslicing = > > > (has_preemption && has_semaphores) || uses_guc_submission; > > > > That works too. Otoh what exactly is the "uses guc submission" flag and > > why do we have that? I've seen media use it as a stand-in for "does the > > kernel want bonded or parallel ctx?". Maybe another thing to check. > > > > Another option, if you really think the feature flag is the best approach > > (because future hw will drop timeslicing for some reason), then debugfs is > > the place of igt-only api. > > Maybe check and potentially remove all I915_SCHEDULER_CAP_.. flags. It could > be another easy pickings with a lot of IGT work type endeavour. Yeah there's a lot unfortunately. I'll make a note internally that we need to look at this again maybe next year, but for now we're going to only concentrate on stuff that has actual architecture/design impact. In the grand scheme of things exporting a bunch of flags for igt in the uapi is mostly harmless. There's much bigger fish to fry were we allow igt to make changes to objects that should be all immutable. Those need to be worked out first. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx