From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.skyhub.de (mail.skyhub.de [5.9.137.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FF5B71 for ; Wed, 16 Jun 2021 10:21:40 +0000 (UTC) Received: from zn.tnic (p200300ec2f0c2b0089cf8396f15d74fc.dip0.t-ipconnect.de [IPv6:2003:ec:2f0c:2b00:89cf:8396:f15d:74fc]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id 541F71EC011B; Wed, 16 Jun 2021 12:21:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1623838899; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=wbasH9F+/8usQ05k7ehXA0ZPHCtfUxj/1yk5NUHjI/Y=; b=XGd52VP22lozejsS94pwDyjBrCcuuDxnBEZ4zJHZ8Lgd4GKdlqlhWY7pIhVdmFvqwrlHaO J+GU5sqe5iFyy+xMGTwn4BqP23Wi4XEValrRrCo3dAjd4UGCGNPtOsO8qGiM1w81mNG++0 Z8fkTJ6wQ3bM9iurbY9vbHFPzAYwvTg= Date: Wed, 16 Jun 2021 12:21:29 +0200 From: Borislav Petkov To: Brijesh Singh Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-efi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-coco@lists.linux.dev, linux-mm@kvack.org, linux-crypto@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Joerg Roedel , Tom Lendacky , "H. Peter Anvin" , Ard Biesheuvel , Paolo Bonzini , Sean Christopherson , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Andy Lutomirski , Dave Hansen , Sergio Lopez , Peter Gonda , Peter Zijlstra , Srinivas Pandruvada , David Rientjes , tony.luck@intel.com, npmccallum@redhat.com Subject: Re: [PATCH Part1 RFC v3 08/22] x86/compressed: Add helper for validating pages in the decompression stage Message-ID: References: <20210602140416.23573-1-brijesh.singh@amd.com> <20210602140416.23573-9-brijesh.singh@amd.com> X-Mailing-List: linux-coco@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20210602140416.23573-9-brijesh.singh@amd.com> On Wed, Jun 02, 2021 at 09:04:02AM -0500, Brijesh Singh wrote: > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index 3ebf00772f26..1424b8ffde0b 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -56,6 +56,25 @@ > #define GHCB_MSR_HV_FT_RESP_VAL(v) \ > (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) > > +#define GHCB_HV_FT_SNP BIT_ULL(0) That define is already added by x86/sev: Check SEV-SNP features support earlier. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette