* [PATCH] phy: uniphier-pcie: Fix updating phy parameters
@ 2021-06-07 3:50 ` Kunihiko Hayashi
0 siblings, 0 replies; 6+ messages in thread
From: Kunihiko Hayashi @ 2021-06-07 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-phy, linux-arm-kernel, linux-kernel, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
The current driver uses a value from register TEST_O as the original
value for register TEST_I, though, the value is overwritten by "param",
so there is a bug that the original value isn't no longer used.
The value of TEST_O[7:0] should be masked with "mask", replaced with
"param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value.
Fixes: c6d9b1324159 ("phy: socionext: add PCIe PHY driver support")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index e4adab3..6bdbd1f 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -24,11 +24,13 @@
#define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
#define PCL_PHY_TEST_I 0x2000
-#define PCL_PHY_TEST_O 0x2004
#define TESTI_DAT_MASK GENMASK(13, 6)
#define TESTI_ADR_MASK GENMASK(5, 1)
#define TESTI_WR_EN BIT(0)
+#define PCL_PHY_TEST_O 0x2004
+#define TESTO_DAT_MASK GENMASK(7, 0)
+
#define PCL_PHY_RESET 0x200c
#define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */
#define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
@@ -77,11 +79,12 @@ static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
val = FIELD_PREP(TESTI_DAT_MASK, 1);
val |= FIELD_PREP(TESTI_ADR_MASK, reg);
uniphier_pciephy_testio_write(priv, val);
- val = readl(priv->base + PCL_PHY_TEST_O);
+ val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK;
/* update value */
- val &= ~FIELD_PREP(TESTI_DAT_MASK, mask);
- val = FIELD_PREP(TESTI_DAT_MASK, mask & param);
+ val &= ~mask;
+ val |= mask & param;
+ val = FIELD_PREP(TESTI_DAT_MASK, val);
val |= FIELD_PREP(TESTI_ADR_MASK, reg);
uniphier_pciephy_testio_write(priv, val);
uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] phy: uniphier-pcie: Fix updating phy parameters
@ 2021-06-07 3:50 ` Kunihiko Hayashi
0 siblings, 0 replies; 6+ messages in thread
From: Kunihiko Hayashi @ 2021-06-07 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-phy, linux-arm-kernel, linux-kernel, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
The current driver uses a value from register TEST_O as the original
value for register TEST_I, though, the value is overwritten by "param",
so there is a bug that the original value isn't no longer used.
The value of TEST_O[7:0] should be masked with "mask", replaced with
"param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value.
Fixes: c6d9b1324159 ("phy: socionext: add PCIe PHY driver support")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index e4adab3..6bdbd1f 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -24,11 +24,13 @@
#define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
#define PCL_PHY_TEST_I 0x2000
-#define PCL_PHY_TEST_O 0x2004
#define TESTI_DAT_MASK GENMASK(13, 6)
#define TESTI_ADR_MASK GENMASK(5, 1)
#define TESTI_WR_EN BIT(0)
+#define PCL_PHY_TEST_O 0x2004
+#define TESTO_DAT_MASK GENMASK(7, 0)
+
#define PCL_PHY_RESET 0x200c
#define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */
#define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
@@ -77,11 +79,12 @@ static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
val = FIELD_PREP(TESTI_DAT_MASK, 1);
val |= FIELD_PREP(TESTI_ADR_MASK, reg);
uniphier_pciephy_testio_write(priv, val);
- val = readl(priv->base + PCL_PHY_TEST_O);
+ val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK;
/* update value */
- val &= ~FIELD_PREP(TESTI_DAT_MASK, mask);
- val = FIELD_PREP(TESTI_DAT_MASK, mask & param);
+ val &= ~mask;
+ val |= mask & param;
+ val = FIELD_PREP(TESTI_DAT_MASK, val);
val |= FIELD_PREP(TESTI_ADR_MASK, reg);
uniphier_pciephy_testio_write(priv, val);
uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN);
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] phy: uniphier-pcie: Fix updating phy parameters
@ 2021-06-07 3:50 ` Kunihiko Hayashi
0 siblings, 0 replies; 6+ messages in thread
From: Kunihiko Hayashi @ 2021-06-07 3:50 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Vinod Koul
Cc: linux-phy, linux-arm-kernel, linux-kernel, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
The current driver uses a value from register TEST_O as the original
value for register TEST_I, though, the value is overwritten by "param",
so there is a bug that the original value isn't no longer used.
The value of TEST_O[7:0] should be masked with "mask", replaced with
"param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value.
Fixes: c6d9b1324159 ("phy: socionext: add PCIe PHY driver support")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/phy/socionext/phy-uniphier-pcie.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index e4adab3..6bdbd1f 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -24,11 +24,13 @@
#define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
#define PCL_PHY_TEST_I 0x2000
-#define PCL_PHY_TEST_O 0x2004
#define TESTI_DAT_MASK GENMASK(13, 6)
#define TESTI_ADR_MASK GENMASK(5, 1)
#define TESTI_WR_EN BIT(0)
+#define PCL_PHY_TEST_O 0x2004
+#define TESTO_DAT_MASK GENMASK(7, 0)
+
#define PCL_PHY_RESET 0x200c
#define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */
#define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */
@@ -77,11 +79,12 @@ static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
val = FIELD_PREP(TESTI_DAT_MASK, 1);
val |= FIELD_PREP(TESTI_ADR_MASK, reg);
uniphier_pciephy_testio_write(priv, val);
- val = readl(priv->base + PCL_PHY_TEST_O);
+ val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK;
/* update value */
- val &= ~FIELD_PREP(TESTI_DAT_MASK, mask);
- val = FIELD_PREP(TESTI_DAT_MASK, mask & param);
+ val &= ~mask;
+ val |= mask & param;
+ val = FIELD_PREP(TESTI_DAT_MASK, val);
val |= FIELD_PREP(TESTI_ADR_MASK, reg);
uniphier_pciephy_testio_write(priv, val);
uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN);
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] phy: uniphier-pcie: Fix updating phy parameters
2021-06-07 3:50 ` Kunihiko Hayashi
(?)
@ 2021-06-21 6:33 ` Vinod Koul
-1 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-06-21 6:33 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Kishon Vijay Abraham I, linux-phy, linux-arm-kernel,
linux-kernel, Masami Hiramatsu, Jassi Brar
On 07-06-21, 12:50, Kunihiko Hayashi wrote:
> The current driver uses a value from register TEST_O as the original
> value for register TEST_I, though, the value is overwritten by "param",
> so there is a bug that the original value isn't no longer used.
>
> The value of TEST_O[7:0] should be masked with "mask", replaced with
> "param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] phy: uniphier-pcie: Fix updating phy parameters
@ 2021-06-21 6:33 ` Vinod Koul
0 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-06-21 6:33 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Kishon Vijay Abraham I, linux-phy, linux-arm-kernel,
linux-kernel, Masami Hiramatsu, Jassi Brar
On 07-06-21, 12:50, Kunihiko Hayashi wrote:
> The current driver uses a value from register TEST_O as the original
> value for register TEST_I, though, the value is overwritten by "param",
> so there is a bug that the original value isn't no longer used.
>
> The value of TEST_O[7:0] should be masked with "mask", replaced with
> "param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value.
Applied, thanks
--
~Vinod
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] phy: uniphier-pcie: Fix updating phy parameters
@ 2021-06-21 6:33 ` Vinod Koul
0 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2021-06-21 6:33 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Kishon Vijay Abraham I, linux-phy, linux-arm-kernel,
linux-kernel, Masami Hiramatsu, Jassi Brar
On 07-06-21, 12:50, Kunihiko Hayashi wrote:
> The current driver uses a value from register TEST_O as the original
> value for register TEST_I, though, the value is overwritten by "param",
> so there is a bug that the original value isn't no longer used.
>
> The value of TEST_O[7:0] should be masked with "mask", replaced with
> "param", and placed in the bitfield TESTI_DAT_MASK as new TEST_I value.
Applied, thanks
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-06-21 6:34 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2021-06-07 3:50 [PATCH] phy: uniphier-pcie: Fix updating phy parameters Kunihiko Hayashi
2021-06-07 3:50 ` Kunihiko Hayashi
2021-06-07 3:50 ` Kunihiko Hayashi
2021-06-21 6:33 ` Vinod Koul
2021-06-21 6:33 ` Vinod Koul
2021-06-21 6:33 ` Vinod Koul
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