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Thu, 24 Jun 2021 13:50:58 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEFE4C061760 for ; Thu, 24 Jun 2021 10:48:38 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id h1so3356143plt.1 for ; Thu, 24 Jun 2021 10:48:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=J4PJUucpibDnG3QpPqzDVfqLhw0sdHSMYuZQn4I2GAw=; b=WcJUtvqFiotpP7LSYJMlPARdJr+vmPdZmJ3Cp/Vlgpu+MbvlDBEScPrY1fBz5rPVlP 1+1xwug16fD5GxLSoUgeWG3S2qMKjf7ZEWdHxad7R9iN7dynCxnVkDbxl0cXfqjnq+yw RFOCK8qMu3zCam96waIjGa/FuusCTKO7/umt4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=J4PJUucpibDnG3QpPqzDVfqLhw0sdHSMYuZQn4I2GAw=; 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charset=utf-8 Content-Disposition: inline In-Reply-To: <20210624115813.3613290-2-thara.gopinath@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, Jun 24, 2021 at 07:58:09AM -0400, Thara Gopinath wrote: > Introduce SCM calls to access/configure limits management hardware(LMH). > > Signed-off-by: Thara Gopinath > --- > > v1->v2: > Changed the input parameters in qcom_scm_lmh_dcvsh from payload_buf and > payload_size to payload_fn, payload_reg, payload_val as per Bjorn's review > comments. > > drivers/firmware/qcom_scm.c | 54 +++++++++++++++++++++++++++++++++++++ > drivers/firmware/qcom_scm.h | 4 +++ > include/linux/qcom_scm.h | 14 ++++++++++ > 3 files changed, 72 insertions(+) > > diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c > index ee9cb545e73b..19e9fb91d084 100644 > --- a/drivers/firmware/qcom_scm.c > +++ b/drivers/firmware/qcom_scm.c > @@ -1147,6 +1147,60 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en) > } > EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); > > +bool qcom_scm_lmh_dcvsh_available(void) > +{ > + return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); > +} > +EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); > + > +int qcom_scm_lmh_profile_change(u32 profile_id) > +{ > + struct qcom_scm_desc desc = { > + .svc = QCOM_SCM_SVC_LMH, > + .cmd = QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE, > + .arginfo = QCOM_SCM_ARGS(1, QCOM_SCM_VAL), > + .args[0] = profile_id, > + .owner = ARM_SMCCC_OWNER_SIP, > + }; > + > + return qcom_scm_call(__scm->dev, &desc, NULL); > +} > +EXPORT_SYMBOL(qcom_scm_lmh_profile_change); > + > +int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, > + u64 limit_node, u32 node_id, u64 version) > +{ > + dma_addr_t payload_phys; > + u32 *payload_buf; > + int payload_size = 5 * sizeof(u32); > + > + struct qcom_scm_desc desc = { > + .svc = QCOM_SCM_SVC_LMH, > + .cmd = QCOM_SCM_LMH_LIMIT_DCVSH, > + .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_VAL, > + QCOM_SCM_VAL, QCOM_SCM_VAL), > + .args[1] = payload_size, > + .args[2] = limit_node, > + .args[3] = node_id, > + .args[4] = version, > + .owner = ARM_SMCCC_OWNER_SIP, > + }; > + > + payload_buf = dma_alloc_coherent(__scm->dev, payload_size, &payload_phys, GFP_KERNEL); > + if (!payload_buf) > + return -ENOMEM; > + > + payload_buf[0] = payload_fn; > + payload_buf[1] = 0; > + payload_buf[2] = payload_reg; > + payload_buf[3] = 1; > + payload_buf[4] = payload_val; > + > + desc.args[0] = payload_phys; > + return qcom_scm_call(__scm->dev, &desc, NULL); dma_free_coherent()?