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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id e3sm3750368pfi.189.2021.08.04.11.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Aug 2021 11:31:52 -0700 (PDT) Date: Wed, 4 Aug 2021 18:31:48 +0000 From: Sean Christopherson To: Kuppuswamy Sathyanarayanan Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Peter Zijlstra , Andy Lutomirski , Peter H Anvin , Dave Hansen , Tony Luck , Dan Williams , Andi Kleen , Kirill Shutemov , Kuppuswamy Sathyanarayanan , x86@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 11/12] x86/tdx: Don't write CSTAR MSR on Intel Message-ID: References: <20210804181329.2899708-1-sathyanarayanan.kuppuswamy@linux.intel.com> <20210804181329.2899708-12-sathyanarayanan.kuppuswamy@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210804181329.2899708-12-sathyanarayanan.kuppuswamy@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 04, 2021, Kuppuswamy Sathyanarayanan wrote: > From: Andi Kleen > > On Intel CPUs writing the CSTAR MSR is not really needed. Syscalls > from 32bit work using SYSENTER and 32bit SYSCALL is an illegal opcode. > But the kernel did write it anyways even though it was ignored by > the CPU. Inside a TDX guest this actually leads to a #GP. While the #GP > is caught and recovered from, it prints an ugly message at boot. > Do not write the CSTAR MSR on Intel CPUs. Not that it really matters, but... Is #GP the actual TDX-Module behavior? If so, isn't that a contradiction with respect to the TDX-Module architecture? It says: guest TD access violations to MSRs can cause a #GP(0) in most cases where the MSR is enumerated as inaccessible by the Intel TDX module via CPUID virtualization. In other cases, guest TD access violations to MSRs can cause a #VE. Given that there is no dedicated CPUID flag for CSTAR and CSTAR obviously exists on Intel CPUs, I don't see how the TDX-Module can possible enumerate CSTAR as being inaccessible. Regardless of #GP versus #VE, "Table 16.2 MSR Virtualization" needs to state the actual behavior.