From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Sibi Sankar <sibis@codeaurora.org>
Cc: sboyd@kernel.org, robh+dt@kernel.org, mka@chromium.org,
viresh.kumar@linaro.org, agross@kernel.org, rjw@rjwysocki.net,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
dianders@chromium.org, tdas@codeaurora.org
Subject: Re: [PATCH 4/4] arm64: dts: qcom: sm8350: Fixup the cpufreq node
Date: Wed, 4 Aug 2021 17:59:04 -0500 [thread overview]
Message-ID: <YQsbuN1xyAlCYRqK@builder.lan> (raw)
In-Reply-To: <1627581885-32165-5-git-send-email-sibis@codeaurora.org>
On Thu 29 Jul 13:04 CDT 2021, Sibi Sankar wrote:
> Fixup the register regions used by the cpufreq node on SM8350 SoC to
> support per core L3 DCVS.
>
That sounds good, but why are you dropping the platform-specific
compatible?
Regards,
Bjorn
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index a631d58166b1..d0a5a5568602 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -967,11 +967,10 @@
> };
>
> cpufreq_hw: cpufreq@18591000 {
> - compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
> - reg = <0 0x18591000 0 0x1000>,
> - <0 0x18592000 0 0x1000>,
> - <0 0x18593000 0 0x1000>;
> - reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
> + compatible = "qcom,cpufreq-epss";
> + reg = <0 0x18591100 0 0x900>,
> + <0 0x18592100 0 0x900>,
> + <0 0x18593100 0 0x900>;
>
> clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> clock-names = "xo", "alternate";
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
next prev parent reply other threads:[~2021-08-04 22:59 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-29 18:04 [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Sibi Sankar
2021-07-29 18:04 ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Sibi Sankar
2021-08-03 19:23 ` Rob Herring
2021-08-04 18:56 ` Stephen Boyd
2021-07-29 18:04 ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
2021-08-04 19:01 ` Stephen Boyd
2021-08-05 17:47 ` Sibi Sankar
2021-08-05 18:25 ` Stephen Boyd
2021-08-06 6:42 ` Sibi Sankar
2021-08-04 23:11 ` Bjorn Andersson
2021-08-04 23:20 ` Bjorn Andersson
2021-07-29 18:04 ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
2021-08-04 18:57 ` Stephen Boyd
2021-08-31 15:30 ` Matthias Kaehlcke
2021-08-31 17:04 ` Bjorn Andersson
2021-09-06 3:20 ` Sibi Sankar
2021-09-07 19:14 ` Doug Anderson
2021-07-29 18:04 ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Sibi Sankar
2021-08-04 22:59 ` Bjorn Andersson [this message]
2021-08-04 23:58 ` Matthias Kaehlcke
2021-08-30 6:47 ` Sibi Sankar
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