From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F3A7C432BE for ; Tue, 17 Aug 2021 18:42:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2903E604AC for ; Tue, 17 Aug 2021 18:42:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233610AbhHQSnF (ORCPT ); Tue, 17 Aug 2021 14:43:05 -0400 Received: from mail-ot1-f47.google.com ([209.85.210.47]:34335 "EHLO mail-ot1-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233546AbhHQSnC (ORCPT ); Tue, 17 Aug 2021 14:43:02 -0400 Received: by mail-ot1-f47.google.com with SMTP id e13-20020a9d63cd0000b02904fa42f9d275so26114858otl.1; Tue, 17 Aug 2021 11:42:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=t12bYEBWi0z4wmn6e6NLudRTxxoZl2hQIUrRPCOM8Q4=; b=skuihdxEcBY/1D9rEkCR9HwV36dBgKVjiH9DxAKXGhsYTmOgTcuHGDk8OLSRTRwC7j vR+tezt+NuAThQmx7+WboRDvwQwdZK6xx1rs/LNghom0DZ+0Quf/EbhBTxzwQvSSxGQK +mZNLBlXE8NeX3q8NymjjvpcC7aNE6Xw2Ad/tpQx5Pc+9kFAH+2GmXJzLcS49p/tkR69 KLr2BflARkCJ8v/jlF+7CCB8KXjQqp89UmNLBbQgXWwnrF9AYlgdrFUAzet7p3x+Pjih 0Qji/u4BcZIijtMVC3Jk3nyOkRP/4GXRK62Oj/t7bchKKQfPI7QVI3pYN1YUwVCOBSsF G6vg== X-Gm-Message-State: AOAM531QZqo7+vwwB5LbmVOPrE9C8io4khoXrCvN8GntP9o/3jsNToZl 6aHW6XfBaQtYvmPSimn1Kw== X-Google-Smtp-Source: ABdhPJyCXj4v1SFKlL3zbu1pyq/qO7MurDY6wV3I33NhP8P34saidcSdVm4f636dw43lzo+g5tav0A== X-Received: by 2002:a05:6830:2a08:: with SMTP id y8mr3835309otu.61.1629225748122; Tue, 17 Aug 2021 11:42:28 -0700 (PDT) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id a19sm554079otl.48.2021.08.17.11.42.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Aug 2021 11:42:27 -0700 (PDT) Received: (nullmailer pid 632074 invoked by uid 1000); Tue, 17 Aug 2021 18:42:25 -0000 Date: Tue, 17 Aug 2021 13:42:25 -0500 From: Rob Herring To: Sam Protsenko Cc: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?B?UGF3ZcWC?= Chmiel , Chanwoo Choi , Linus Walleij , Tomasz Figa , Marc Zyngier , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Message-ID: References: <20210811114827.27322-1-semen.protsenko@linaro.org> <20210811114827.27322-8-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210811114827.27322-8-semen.protsenko@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, Aug 11, 2021 at 02:48:27PM +0300, Sam Protsenko wrote: > Samsung Exynos850 is ARMv8-based mobile-oriented SoC. > > This patch adds minimal SoC support by including next Device Tree nodes: > > 1. Octa cores (Cortex-A55), supporting PSCI v1.0 > 2. ARM architecture timer (armv8-timer) > 3. Interrupt controller (GIC-400) > 4. Pinctrl nodes for GPIO > 5. Serial node > > Signed-off-by: Sam Protsenko > --- > Changes in v3: > - Used generic fixed clock for serial > > Changes in v2: > * Commit message: > - Documented added dts features instead of CPU features > > * exynos850-usi.dtsi: > - Removed, moved everything to exynos850.dtsi > > * exynos850.dtsi: > - Root node: > - Added comment about engineering name (Exynos3830) > - Renamed pinctrl nodes, adding domain names > - Used hard coded IRQ numbers instead of named constants everywhere > - Added soc node, moved next nodes there: gic, clock, pinctrls and > serial > - Used address-cells=1 for soc node and removed unneeded 0x0 from > reg properties > - Moved exynos850-pinctrl.dtsi include line to the end of > exynos850.dtsi > - Coding style fixes > - cpus: > - Used address-cells=1 for cpus node > - Renamed cpu@0001 to cpu@1, and so on > - Left only "arm,cortex-a55" for cpus compatible > - Renamed reg = <0x0001> to <0x1> for cpus > - armv8 timer: > - Add comment about missing HV timer IRQ to armv8 timer node > - Removed not existing properties from armv8 timer node > - Fixed cpu number in CPU_MASK() > - Removed obsolete clock-frequency property > - GIC: > - Fixed GIC type to be GIC-400 > - Fixed size of GIC's 2nd region to be 0x2000 > - serial node: > - Hard coded clock number for serial_0 for now; will replace with > named const once proper clock driver is implemented > - Removed gate_uart_clk0 clock from serial_0, as that clock is not > supported in serial driver anyway (yet) > - clock node: > - Fixed clock controller node name (@0x12.. -> @12..) > > * exynos850-pinctrl.dtsi: > - Referenced pinctrl nodes instead of defining those again in root node > - Fixed interrupt-cells (3 -> 2) > - Fixed USI related comments for pin config nodes > - Removed decon_f_te_* and fm_lna_en nodes (won't be used) > - Reordered pin config nodes by pin numbers > - Improved all comments > - Used existing named constants for pin-function and pin-pud > - Fixed node names (used hyphens instead of underscore) > - Fixed warnings found in W=1 build > > .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++ > arch/arm64/boot/dts/exynos/exynos850.dtsi | 261 ++++++ > 2 files changed, 1009 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi > > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > new file mode 100644 > index 000000000000..ba5d5f33e2f6 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > @@ -0,0 +1,748 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source > + * > + * Copyright (C) 2017 Samsung Electronics Co., Ltd. > + * Copyright (C) 2021 Linaro Ltd. > + * > + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device > + * tree nodes in this file. > + */ > + > +#include > +#include > + > +&pinctrl_alive { > + gpa0: gpa0 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa1: gpa1 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa2: gpa2 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa3: gpa3 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa4: gpa4 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + gpq0: gpq0 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ > + i2c5_bus: i2c5-bus { Please name all the pinctrl nodes with some pattern you can match on once there is a schema. '-pins$' is my suggestion. > + samsung,pins = "gpa3-5", "gpa3-6"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = <0>; > + }; > + > + /* I2C6 (also called MOTOR_I2C in TRM) */ > + i2c6_bus: i2c6-bus { > + samsung,pins = "gpa3-7", "gpa4-0"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = <0>; > + }; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CF51C4338F for ; Tue, 17 Aug 2021 18:44:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C6F7604AC for ; Tue, 17 Aug 2021 18:44:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2C6F7604AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4keoKL+Denfo+QWP7beGRcsmF0/dOspCswjYM1PDYSM=; b=n/qAxSgckH4oOh fnLCsS++9brx105g5WWXYMZwAgnh5YmR4ZOE0fFHJkNiTNUGU299ocq8Ja4JH71Oz4g9qMLvnR902 J8j19QlIJM5ES2YW6WCHr778IM0LcfjPY6bsE2wpwxM7g5u2Cn4keBaT3c2id3FALL/Blx1HzuuDu ThSDqiYYtxFq0FexxxnLm/6aAirnpm5UgKJLfhjWmpWNCTkobZXZdyodcOmymIUnGYF9TFOMRK/7i jwaFEf+vxGgMElBagO9VFubXHJRM2ZIQldPQXZKBnnhV+p8N3gEBPjY5Vb6808SuerBbd6tJ6ZVp+ 7uOOHX6AmkP8sBKd/DDQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mG42l-003FZ3-5e; Tue, 17 Aug 2021 18:42:35 +0000 Received: from mail-ot1-f43.google.com ([209.85.210.43]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mG42g-003FXZ-6D for linux-arm-kernel@lists.infradead.org; Tue, 17 Aug 2021 18:42:32 +0000 Received: by mail-ot1-f43.google.com with SMTP id 108-20020a9d01750000b029050e5cc11ae3so26049394otu.5 for ; Tue, 17 Aug 2021 11:42:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=t12bYEBWi0z4wmn6e6NLudRTxxoZl2hQIUrRPCOM8Q4=; b=ZNXRrIFvNg9Vvi1l0qJ1TYGpedtp8fxsynLZqR614w/WcMbkSwkaoKT69gl9WX4ZF/ 8CMUK2jsymQHtjknh1mK9yVvrL/fNef19b9ZhvrhQo4LkmwpQIxFhVJFIam7gBWf7ZxZ ymU4mLmQUmn3IzaUUvb4/E93/KaOqEp+hYqyGeqsUE6g8MNTCJXjc1SlqzGIS06Y/mI2 mIFaPSZbSCQRVEYlyhxWX8/1v1B+8d7HJTUrcFFUjrYkEUj+HvoE/Q/2tmq1OSE1XMgg D6d5W6DWKjV6E4BR+9TZ5G/lVw3d1BPVxAi7b5MxpissbbA6xwczx2fNC2q9IkqCzWAL W9Lw== X-Gm-Message-State: AOAM532BDRAI7hArXZRKjFd2lxZ3H8h1L+gcrMH3IA5xezzoqe/BKgXo Ym5WFjVXMWEUOE2ApUuHAw== X-Google-Smtp-Source: ABdhPJyCXj4v1SFKlL3zbu1pyq/qO7MurDY6wV3I33NhP8P34saidcSdVm4f636dw43lzo+g5tav0A== X-Received: by 2002:a05:6830:2a08:: with SMTP id y8mr3835309otu.61.1629225748122; Tue, 17 Aug 2021 11:42:28 -0700 (PDT) Received: from robh.at.kernel.org (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id a19sm554079otl.48.2021.08.17.11.42.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Aug 2021 11:42:27 -0700 (PDT) Received: (nullmailer pid 632074 invoked by uid 1000); Tue, 17 Aug 2021 18:42:25 -0000 Date: Tue, 17 Aug 2021 13:42:25 -0500 From: Rob Herring To: Sam Protsenko Cc: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?B?UGF3ZcWC?= Chmiel , Chanwoo Choi , Linus Walleij , Tomasz Figa , Marc Zyngier , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Message-ID: References: <20210811114827.27322-1-semen.protsenko@linaro.org> <20210811114827.27322-8-semen.protsenko@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210811114827.27322-8-semen.protsenko@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210817_114230_282232_6648DD89 X-CRM114-Status: GOOD ( 30.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 11, 2021 at 02:48:27PM +0300, Sam Protsenko wrote: > Samsung Exynos850 is ARMv8-based mobile-oriented SoC. > > This patch adds minimal SoC support by including next Device Tree nodes: > > 1. Octa cores (Cortex-A55), supporting PSCI v1.0 > 2. ARM architecture timer (armv8-timer) > 3. Interrupt controller (GIC-400) > 4. Pinctrl nodes for GPIO > 5. Serial node > > Signed-off-by: Sam Protsenko > --- > Changes in v3: > - Used generic fixed clock for serial > > Changes in v2: > * Commit message: > - Documented added dts features instead of CPU features > > * exynos850-usi.dtsi: > - Removed, moved everything to exynos850.dtsi > > * exynos850.dtsi: > - Root node: > - Added comment about engineering name (Exynos3830) > - Renamed pinctrl nodes, adding domain names > - Used hard coded IRQ numbers instead of named constants everywhere > - Added soc node, moved next nodes there: gic, clock, pinctrls and > serial > - Used address-cells=1 for soc node and removed unneeded 0x0 from > reg properties > - Moved exynos850-pinctrl.dtsi include line to the end of > exynos850.dtsi > - Coding style fixes > - cpus: > - Used address-cells=1 for cpus node > - Renamed cpu@0001 to cpu@1, and so on > - Left only "arm,cortex-a55" for cpus compatible > - Renamed reg = <0x0001> to <0x1> for cpus > - armv8 timer: > - Add comment about missing HV timer IRQ to armv8 timer node > - Removed not existing properties from armv8 timer node > - Fixed cpu number in CPU_MASK() > - Removed obsolete clock-frequency property > - GIC: > - Fixed GIC type to be GIC-400 > - Fixed size of GIC's 2nd region to be 0x2000 > - serial node: > - Hard coded clock number for serial_0 for now; will replace with > named const once proper clock driver is implemented > - Removed gate_uart_clk0 clock from serial_0, as that clock is not > supported in serial driver anyway (yet) > - clock node: > - Fixed clock controller node name (@0x12.. -> @12..) > > * exynos850-pinctrl.dtsi: > - Referenced pinctrl nodes instead of defining those again in root node > - Fixed interrupt-cells (3 -> 2) > - Fixed USI related comments for pin config nodes > - Removed decon_f_te_* and fm_lna_en nodes (won't be used) > - Reordered pin config nodes by pin numbers > - Improved all comments > - Used existing named constants for pin-function and pin-pud > - Fixed node names (used hyphens instead of underscore) > - Fixed warnings found in W=1 build > > .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++ > arch/arm64/boot/dts/exynos/exynos850.dtsi | 261 ++++++ > 2 files changed, 1009 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi > > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > new file mode 100644 > index 000000000000..ba5d5f33e2f6 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > @@ -0,0 +1,748 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source > + * > + * Copyright (C) 2017 Samsung Electronics Co., Ltd. > + * Copyright (C) 2021 Linaro Ltd. > + * > + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device > + * tree nodes in this file. > + */ > + > +#include > +#include > + > +&pinctrl_alive { > + gpa0: gpa0 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa1: gpa1 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa2: gpa2 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa3: gpa3 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + gpa4: gpa4 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupt-parent = <&gic>; > + interrupts = , > + , > + , > + ; > + }; > + > + gpq0: gpq0 { > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ > + i2c5_bus: i2c5-bus { Please name all the pinctrl nodes with some pattern you can match on once there is a schema. '-pins$' is my suggestion. > + samsung,pins = "gpa3-5", "gpa3-6"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = <0>; > + }; > + > + /* I2C6 (also called MOTOR_I2C in TRM) */ > + i2c6_bus: i2c6-bus { > + samsung,pins = "gpa3-7", "gpa4-0"; > + samsung,pin-function = ; > + samsung,pin-pud = ; > + samsung,pin-drv = <0>; > + }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel