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Tue, 31 Aug 2021 22:30:47 -0400 (EDT) Date: Tue, 31 Aug 2021 21:30:45 -0500 From: Patrick Williams To: pdel@fb.com Subject: Re: [PATCH 1/1] hw/arm/aspeed: Allow machine to set serial_hd(0) Message-ID: References: <20210831233140.2659116-1-pdel@fb.com> <20210831233140.2659116-2-pdel@fb.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="C6Lm7KwueyVOnR8v" Content-Disposition: inline In-Reply-To: <20210831233140.2659116-2-pdel@fb.com> Received-SPF: pass client-ip=66.111.4.27; envelope-from=patrick@stwcx.xyz; helo=out3-smtp.messagingengine.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.499, PDS_OTHER_BAD_TLD=1.999, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@aj.id.au, f4bug@amsat.org, qemu-arm@nongnu.org, clg@kaod.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --C6Lm7KwueyVOnR8v Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Aug 31, 2021 at 04:31:40PM -0700, pdel@fb.com wrote: > From: Peter Delevoryas >=20 > When you run QEMU with an Aspeed machine and a single serial device > using stdio like this: >=20 > qemu -machine ast2600-evb -drive ... -serial stdio >=20 > The guest OS can read and write to the UART5 registers at 0x1E784000 and > it will receive from stdin and write to stdout. The Aspeed SoC's have a > lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on > the board design, may be using any of them as the serial console. (See > "stdout-path" in a DTS to check which one is chosen). >=20 > Most boards, including all of those currently defined in > hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds > some flexibility for different boards without requiring users to change > their command-line invocation of QEMU. >=20 > I tested this doesn't break existing code by booting an AST2500 OpenBMC > image and an AST2600 OpenBMC image, each using UART5 as the console. >=20 > Then I tested switching the default to UART1 and booting an AST2600 > OpenBMC image that uses UART1, and that worked too. >=20 > Signed-off-by: Peter Delevoryas > --- > hw/arm/aspeed.c | 1 + > hw/arm/aspeed_ast2600.c | 11 +++++++---- > hw/arm/aspeed_soc.c | 9 ++++++--- > include/hw/arm/aspeed.h | 1 + > 4 files changed, 15 insertions(+), 7 deletions(-) >=20 Reviewed-by: Patrick Williams --=20 Patrick Williams --C6Lm7KwueyVOnR8v Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEBGD9ii4LE9cNbqJBqwNHzC0AwRkFAmEu5dMACgkQqwNHzC0A wRn3kQ//ULzm12CH3hiEdGlHYWspj3kB6hcCB/1LIG81I2mx/GUClYF8RQ3qoJxy MI1l/DVfV5PnHZrPuHaulenlZWKaQyjDVCLbMjbzAUZSEtXiGq8+1vrdAfVMT3ef oQllpSl97eAVK97acerKZ63h7qjkAsuq07H3E6ij9po+DblVYhQisCAHwcl7lKVq EpWgbjvitLI7/ns1PziWcL0V6nrL1SNHQ6UCHFDfOSCa73LvAJ6nHSqmeH3KtMGi 5aCVT1aOO+6QbU3BZxlXgzNfIqFFnSxjdiT2OKqJ4C5XM+f1zZz3+5QR56Rpl58d RoL+RK6rTYK6z06MPArStnB7ZN82BCY9yPoGDYJybLczvi5PhPsKHj1hcYsGT1OO GfHtHBtS7CzVVyv8sdp8M1POK4BYzSFo/YNFG2t3IQ09lfORak06xn3ORPM3ybe1 ftli6J4DfpplEQD6MHAqdxEmSzi6+BszLezsoEQSIm8a1rfs7OARu3OcsbkSVVsF t/UdeU5x5YYbeKGSnWb9c2IQLOtbQgHH34qU5m0eFPrj4c86KCnsJ18lVkSdJDOZ fdv3rsfE1Zoy4ncu23077FKgSjHQ/u8oW032FTVb9akp6e3SR9VhY+vzMBAd84mf 5OzJdG8mkKwX9OYOLy7vZtqeWebYrTvzOxBnaOdaBlKYQ6VjkFQ= =ToJ2 -----END PGP SIGNATURE----- --C6Lm7KwueyVOnR8v--