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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id j17sm2413677ots.10.2021.09.07.06.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Sep 2021 06:46:57 -0700 (PDT) Date: Tue, 7 Sep 2021 06:47:57 -0700 From: Bjorn Andersson To: AngeloGioacchino Del Regno Cc: agross@kernel.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org Subject: Re: [PATCH 7/7] arm64: dts: qcom: msm8998-xperia: Add audio clock and its pin Message-ID: References: <20210903180924.1006044-1-angelogioacchino.delregno@somainline.org> <20210903180924.1006044-7-angelogioacchino.delregno@somainline.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210903180924.1006044-7-angelogioacchino.delregno@somainline.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 03 Sep 11:09 PDT 2021, AngeloGioacchino Del Regno wrote: > All smartphones of this platform are equipped with a WCD9335 audio > codec, getting its MCLK from PM8998 gpio13: add this clock to DT. > > Signed-off-by: AngeloGioacchino Del Regno > Reviewed-by: Marijn Suijten > --- > .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > index 5fbe5abf4133..7aeebd3b2e9e 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > @@ -20,6 +20,19 @@ / { > qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ > qcom,board-id = <8 0>; > > + clocks { > + compatible = "simple-bus"; > + > + div1_mclk: divclk1 { > + compatible = "gpio-gate-clock"; > + pinctrl-0 = <&audio_mclk_pin>; > + pinctrl-names = "default"; > + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; What controls the clock rate of divclk1? Regards, Bjorn > + #clock-cells = <0>; > + enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; > + }; > + }; > + > board_vbat: vbat-regulator { > compatible = "regulator-fixed"; > regulator-name = "VBAT"; > @@ -313,6 +326,12 @@ cam_snapshot_pin_a: cam-snapshot-btn-active { > input-enable; > qcom,drive-strength = ; > }; > + > + audio_mclk_pin: audio-mclk-pin-active { > + pins = "gpio13"; > + function = "func2"; > + power-source = <0>; > + }; > }; > > &pmi8998_gpio { > -- > 2.32.0 >