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Tue, 14 Sep 2021 11:30:17 +0000 Date: Tue, 14 Sep 2021 14:30:16 +0300 From: Abel Vesa To: Jacky Bai Cc: shawnguo@kernel.org, robh+dt@kernel.org, sboyd@kernel.org, s.hauer@pengutronix.de, p.zabel@pengutronix.de, kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org Subject: Re: [PATCH v3 3/9] clk: imx: Update the compsite driver to support imx8ulp Message-ID: References: <20210914065208.3582128-1-ping.bai@nxp.com> <20210914065208.3582128-4-ping.bai@nxp.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210914065208.3582128-4-ping.bai@nxp.com> X-ClientProxiedBy: VI1PR09CA0114.eurprd09.prod.outlook.com (2603:10a6:803:78::37) To VI1PR0401MB2559.eurprd04.prod.outlook.com (2603:10a6:800:57::8) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ryzen (188.25.164.198) by VI1PR09CA0114.eurprd09.prod.outlook.com (2603:10a6:803:78::37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?WvRtprwdNKJH/q7qjAGk7qK9BvF8fLG9iwpDxhSkQJjn/cSophc2X5RTZw2e?= =?us-ascii?Q?jfuvpJJAnHKSmAfHAYGmBN1+aX0knXgtgAQ9d1erUYI6cjx5GUNHwDlfpN/Q?= =?us-ascii?Q?tMqs8whRzWC0bvPUquXOkHdX5dtIa2tyjqYg/Lo44NWmuyTFgi/S0lSRpDQx?= =?us-ascii?Q?OTnubSSAK/Yha8tehUUI1W7oYyhzhFOoLCh54KV7uztHoukm7l9rccFF1GCQ?= =?us-ascii?Q?cdCE5zOOQn12Paikyk/D74uNV6DVaLv5s2rn/GOXXgBqsbZy8Adgtq1Sdlvn?= =?us-ascii?Q?RkT0BZ4WT2aS0vmIA4YGECKKEModEZbwZQ+ut49HqmfVjxlqRuvhMTC3q7dM?= =?us-ascii?Q?Ky8iNnEaZuAI9wkuNtY8/GxZ6cF87GxKv3/Y0Fx2IKrXd6lK24Yt0ULWi9w1?= =?us-ascii?Q?spZfLgUS9xdtaQsuPclbVy0wPgQG0Yu7R9zC2/ivKY/3rGNs7Yq+jOOgmsRZ?= =?us-ascii?Q?27qvWoHbEUqfRk9mDX5HR/3ub0BecP8mmqIFVEownOs4gPhiQBdpWgeeK83F?= =?us-ascii?Q?BPvaj5JeLnz/7o7J1ZqnZqjRirAmQykJehwkhnW53LQ9DorKpbebWvwzXxA0?= =?us-ascii?Q?zHxB4q5ER9GsNsQgg7GohoaBjqPAOsMbMxUrytN0TdL+OCOVHmXQPv+PThM1?= =?us-ascii?Q?ra+z+u0SBaZ468Kk9ajizH05F3EM1Vrhe5WftD0tUwONPWlylpKfPJXA9Dfx?= =?us-ascii?Q?5CVWBpC1CXyWFdO8AONfxe2644dnwycxRAIU+MxQb2wgCTuO52HbPaBV0ST2?= =?us-ascii?Q?oUspBnBGo3R1MmYLPcWC9oBvafPuLJpqtyus1flKmuUEUYkSN5IyounpREZQ?= =?us-ascii?Q?jVwc9POo6wBaWHqfvBIFGYSR1pdpT9h1WcZqM6torLWzF8IvzhYLgjRiZ++N?= =?us-ascii?Q?/dq01Gv/MmLP1xl9tnjIFPDgUbE0D5E7A0e6zkMu0niPzAals4jCpnyBbnXg?= =?us-ascii?Q?fBd9NYG7ds6Df3jgXaylW2U43L5WYlM34TDal2eKYyb5ZM0Ee3fL40KZFDa2?= =?us-ascii?Q?PahU8qIjSEc5f4v76lPG+tiRTCJzo3wQiXcYMoMJG/UoYU64lml7731Lnagk?= =?us-ascii?Q?Zr53CTH93PfgcLLx39lHTsTxrbb5+w9X3Cfq/Azn/v3g3MGe6gKkG7BkuRPP?= =?us-ascii?Q?Bz4e2iEINztBHgMqMRZwZirwjg4sczPVi9wtrywaszH8sa7FLUuWkNaZ3UBi?= =?us-ascii?Q?gfkRBI0RQb5to2DGW5IpJL0jraiAqAsjb/+tfD8hFZ35AXJLgWbyrOJj3KoT?= =?us-ascii?Q?b2qM7heu77kO2jn/Wvm7LlaRbVnIVVldJYwoKPt0RjIwkk1VLqXi0nWjQcYD?= =?us-ascii?Q?IaIiCvs7S3ygfPNDMjCJl2un?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9b9fc82a-c5c9-481a-9711-08d977730730 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0401MB2559.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2021 11:30:17.6844 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: U8PdsfMDr7/isVsVDB6AS5rtR4R4vgmwZtF2Xh4TfOer3dZkAaH84pyqwkUtDHYy3H7bjDXDqxaO7LE0//OPcQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2638 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 21-09-14 14:52:02, Jacky Bai wrote: > On i.MX8ULP, some peripherals have a sw_rst control resides > in the per device PCC clock control register, all others are > same as i.MX7ULP, so update the 7ulp clock composite driver to > support i.MX8ULP to maxmimize the code reuse. > > Signed-off-by: Peng Fan > Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa > --- > v3 changs: no > --- > drivers/clk/imx/clk-composite-7ulp.c | 61 ++++++++++++++++++++++++++-- > drivers/clk/imx/clk.h | 6 +++ > 2 files changed, 64 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c > index d85ba78abbb1..50ed383320bf 100644 > --- a/drivers/clk/imx/clk-composite-7ulp.c > +++ b/drivers/clk/imx/clk-composite-7ulp.c > @@ -23,11 +23,50 @@ > #define PCG_PCD_WIDTH 3 > #define PCG_PCD_MASK 0x7 > > -struct clk_hw *imx7ulp_clk_hw_composite(const char *name, > +#define SW_RST BIT(28) > + > +static int pcc_gate_enable(struct clk_hw *hw) > +{ > + struct clk_gate *gate = to_clk_gate(hw); > + u32 val; > + int ret; > + > + ret = clk_gate_ops.enable(hw); > + if (ret) > + return ret; > + > + /* > + * release the sw reset for peripherals associated with > + * with this pcc clock. > + */ > + val = readl(gate->reg); > + val |= SW_RST; > + writel(val, gate->reg); > + > + return 0; > +} > + > +static void pcc_gate_disable(struct clk_hw *hw) > +{ > + clk_gate_ops.disable(hw); > +} > + > +static int pcc_gate_is_enabled(struct clk_hw *hw) > +{ > + return clk_gate_ops.is_enabled(hw); > +} > + > +static const struct clk_ops pcc_gate_ops = { > + .enable = pcc_gate_enable, > + .disable = pcc_gate_disable, > + .is_enabled = pcc_gate_is_enabled, > +}; > + > +static struct clk_hw *imx_ulp_clk_hw_composite(const char *name, > const char * const *parent_names, > int num_parents, bool mux_present, > bool rate_present, bool gate_present, > - void __iomem *reg) > + void __iomem *reg, bool has_swrst) > { > struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL; > struct clk_fractional_divider *fd = NULL; > @@ -77,7 +116,7 @@ struct clk_hw *imx7ulp_clk_hw_composite(const char *name, > hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, > mux_hw, &clk_mux_ops, fd_hw, > &clk_fractional_divider_ops, gate_hw, > - &clk_gate_ops, CLK_SET_RATE_GATE | > + has_swrst ? &pcc_gate_ops : &clk_gate_ops, CLK_SET_RATE_GATE | > CLK_SET_PARENT_GATE); > if (IS_ERR(hw)) { > kfree(mux); > @@ -87,3 +126,19 @@ struct clk_hw *imx7ulp_clk_hw_composite(const char *name, > > return hw; > } > + > +struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names, > + int num_parents, bool mux_present, bool rate_present, > + bool gate_present, void __iomem *reg) > +{ > + return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present, > + gate_present, reg, false); > +} > + > +struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names, > + int num_parents, bool mux_present, bool rate_present, > + bool gate_present, void __iomem *reg, bool has_swrst) > +{ > + return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present, > + gate_present, reg, has_swrst); > +} > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h > index 3f518559b8f9..a9bcfee7a75b 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -237,6 +237,12 @@ struct clk_hw *imx7ulp_clk_hw_composite(const char *name, > bool rate_present, bool gate_present, > void __iomem *reg); > > +struct clk_hw *imx8ulp_clk_hw_composite(const char *name, > + const char * const *parent_names, > + int num_parents, bool mux_present, > + bool rate_present, bool gate_present, > + void __iomem *reg, bool has_swrst); > + > struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent, > void __iomem *reg, u8 shift, u8 width, > void (*fixup)(u32 *val)); > -- > 2.26.2 >