* [Intel-gfx] [PATCH i-g-t 0/1] Add test for new hw info query
@ 2021-09-15 21:55 John.C.Harrison
2021-09-15 21:55 ` [igt-dev] " John.C.Harrison
2021-09-15 22:26 ` [igt-dev] ✗ Fi.CI.BAT: failure for Add test for new hw info query Patchwork
0 siblings, 2 replies; 11+ messages in thread
From: John.C.Harrison @ 2021-09-15 21:55 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX, John Harrison, Matthew Brost
From: John Harrison <John.C.Harrison@Intel.com>
Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interface.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Rodrigo Vivi (1):
tests/i915/query: Query, parse and validate the hwconfig table
include/drm-uapi/i915_drm.h | 1 +
lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
2021-09-15 21:55 [Intel-gfx] [PATCH i-g-t 0/1] Add test for new hw info query John.C.Harrison
@ 2021-09-15 21:55 ` John.C.Harrison
2021-09-15 22:26 ` [igt-dev] ✗ Fi.CI.BAT: failure for Add test for new hw info query Patchwork
1 sibling, 0 replies; 11+ messages in thread
From: John.C.Harrison @ 2021-09-15 21:55 UTC (permalink / raw)
To: IGT-Dev
Cc: Intel-GFX, Rodrigo Vivi, John Harrison, Slawomir Milczarek,
Matthew Brost
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
include/drm-uapi/i915_drm.h | 1 +
lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index b9632bb2c..ae0c8dfad 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_TABLE 5
/* Must be kept compact -- no holes and well documented */
/**
diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index 000000000..c9961e6bd
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+ INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+ INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
+ INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
+ INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
+ INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
+ INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
+ INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+ INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+ INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+ INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
+ INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
+ INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
+ INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
+ INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
+ INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
+ INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
+ INTEL_HWCONFIG_MAX_RCS, /* 23 */
+ INTEL_HWCONFIG_MAX_CCS, /* 24 */
+ INTEL_HWCONFIG_MAX_VCS, /* 25 */
+ INTEL_HWCONFIG_MAX_VECS, /* 26 */
+ INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+ INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
+ INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
+ INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
+ INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+ INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+ INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
+ INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
+ INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
+ INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
+ INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
+ INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
+ INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+ INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
+ INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
+ INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
+ INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
+ INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
+ INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
+ INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
+ INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
+ INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
+ INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
+ INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
+ INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
+ INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
+ INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
+ INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
+ INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
+ INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
+ INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
+ INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
+ INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
+ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
+ __INTEL_HWCONFIG_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
+};
+
+enum {
+ INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
+ INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
+ INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
+};
+
+#endif /* _INTEL_HWCONFIG_TYPES_H_ */
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 3c791b8ba..1802287e3 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "intel_hwconfig_types.h"
#include <limits.h>
@@ -842,6 +843,170 @@ static void engines(int fd)
free(engines);
}
+static const char * const hwconfig_keys[] = {
+ [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
+ [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
+ [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
+ [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
+ [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
+ [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
+ [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
+ [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
+ [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
+ [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
+ [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
+ [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
+ [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
+ [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
+ [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
+ [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
+ [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
+ [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
+ [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
+ [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
+ [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
+ [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
+ [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
+ [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
+ [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
+ [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
+ [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
+ [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
+ [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
+ [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
+ [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
+ [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
+ [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
+ [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
+ [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
+ [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
+ [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
+ [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
+ [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
+ [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
+ [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
+ [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
+ [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
+ [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
+ [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
+ [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
+ [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
+ [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
+ [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
+ [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
+ [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
+};
+
+static void query_parse_and_validate_hwconfig_table(int i915)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
+ };
+ uint32_t *data, value;
+ int i = 0;
+ int len, j, max_words, table_size;
+
+ igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
+
+ i915_query_items(i915, &item, 1);
+ table_size = item.length;
+ igt_require(table_size > 0);
+
+ data = malloc(table_size);
+ igt_assert(data);
+ memset(data, 0, table_size);
+ item.data_ptr = to_user_pointer(data);
+
+ i915_query_items(i915, &item, 1);
+ igt_assert(item.length == table_size);
+ igt_info("Table size = %d bytes\n", table_size);
+ igt_assert(table_size > 0);
+
+ /* HWConfig table is a list of KLV sets */
+ max_words = table_size / sizeof(uint32_t);
+ igt_assert(max_words * sizeof(uint32_t) == table_size);
+ while (i < max_words) {
+ /* Attribute ID zero is invalid */
+ igt_assert(data[i] > 0);
+ igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
+
+ len = data[i + 1];
+ igt_assert(len > 0);
+ igt_assert((i + 2 + len) <= max_words);
+
+ igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
+
+ value = data[i + 2];
+ switch (data[i]) {
+ case INTEL_HWCONFIG_MEMORY_TYPE:
+ igt_assert(len == 1);
+ switch (value) {
+ case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
+ igt_info("LPDDR4\n");
+ break;
+ case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
+ igt_info("LPDDR5\n");
+ break;
+ default:
+ igt_assert(0);
+ }
+ break;
+
+ case INTEL_HWCONFIG_CACHE_TYPES:
+ igt_assert(len == 1);
+
+#define TEST_CACHE_TYPE(type) \
+ if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
+ value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
+ igt_info(#type); \
+ if (value) \
+ igt_info(", "); \
+ }
+
+ TEST_CACHE_TYPE(L3);
+ TEST_CACHE_TYPE(LLC);
+ TEST_CACHE_TYPE(EDRAM);
+#undef TEST_CACHE_TYPE
+
+ igt_assert(value == 0);
+ igt_info("\n");
+ break;
+
+ default:
+ for (j = i + 2; j < i + 1 + len; j++)
+ igt_info("%d, ", data[j]);
+ igt_info("%d\n", data[j]);
+ }
+
+ /* Advance to next key */
+ i += 2 + len;
+ }
+
+ free(data);
+}
+
igt_main
{
int fd = -1;
@@ -911,6 +1076,9 @@ igt_main
engines(fd);
}
+ igt_subtest("hwconfig_table")
+ query_parse_and_validate_hwconfig_table(fd);
+
igt_fixture {
close(fd);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
@ 2021-09-15 21:55 ` John.C.Harrison
0 siblings, 0 replies; 11+ messages in thread
From: John.C.Harrison @ 2021-09-15 21:55 UTC (permalink / raw)
To: IGT-Dev
Cc: Intel-GFX, Rodrigo Vivi, John Harrison, Slawomir Milczarek,
Matthew Brost
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
include/drm-uapi/i915_drm.h | 1 +
lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
3 files changed, 275 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index b9632bb2c..ae0c8dfad 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_TABLE 5
/* Must be kept compact -- no holes and well documented */
/**
diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index 000000000..c9961e6bd
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+ INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+ INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
+ INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
+ INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
+ INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
+ INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
+ INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+ INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+ INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+ INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
+ INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
+ INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
+ INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
+ INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
+ INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
+ INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
+ INTEL_HWCONFIG_MAX_RCS, /* 23 */
+ INTEL_HWCONFIG_MAX_CCS, /* 24 */
+ INTEL_HWCONFIG_MAX_VCS, /* 25 */
+ INTEL_HWCONFIG_MAX_VECS, /* 26 */
+ INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+ INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
+ INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
+ INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
+ INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+ INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+ INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
+ INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
+ INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
+ INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
+ INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
+ INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
+ INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+ INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
+ INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
+ INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
+ INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
+ INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
+ INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
+ INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
+ INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
+ INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
+ INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
+ INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
+ INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
+ INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
+ INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
+ INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
+ INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
+ INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
+ INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
+ INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
+ INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
+ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
+ __INTEL_HWCONFIG_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
+};
+
+enum {
+ INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
+ INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
+ INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
+};
+
+#endif /* _INTEL_HWCONFIG_TYPES_H_ */
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 3c791b8ba..1802287e3 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "intel_hwconfig_types.h"
#include <limits.h>
@@ -842,6 +843,170 @@ static void engines(int fd)
free(engines);
}
+static const char * const hwconfig_keys[] = {
+ [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
+ [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
+ [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
+ [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
+ [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
+ [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
+ [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
+ [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
+ [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
+ [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
+ [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
+ [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
+ [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
+ [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
+ [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
+ [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
+ [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
+ [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
+ [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
+ [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
+ [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
+ [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
+ [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
+ [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
+ [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
+ [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
+ [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
+ [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
+ [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
+ [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
+ [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
+ [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
+ [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
+ [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
+ [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
+ [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
+ [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
+ [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
+ [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
+ [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
+ [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
+ [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
+ [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
+ [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
+ [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
+ [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
+ [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
+ [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
+ [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
+ [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
+ [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
+};
+
+static void query_parse_and_validate_hwconfig_table(int i915)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
+ };
+ uint32_t *data, value;
+ int i = 0;
+ int len, j, max_words, table_size;
+
+ igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
+
+ i915_query_items(i915, &item, 1);
+ table_size = item.length;
+ igt_require(table_size > 0);
+
+ data = malloc(table_size);
+ igt_assert(data);
+ memset(data, 0, table_size);
+ item.data_ptr = to_user_pointer(data);
+
+ i915_query_items(i915, &item, 1);
+ igt_assert(item.length == table_size);
+ igt_info("Table size = %d bytes\n", table_size);
+ igt_assert(table_size > 0);
+
+ /* HWConfig table is a list of KLV sets */
+ max_words = table_size / sizeof(uint32_t);
+ igt_assert(max_words * sizeof(uint32_t) == table_size);
+ while (i < max_words) {
+ /* Attribute ID zero is invalid */
+ igt_assert(data[i] > 0);
+ igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
+
+ len = data[i + 1];
+ igt_assert(len > 0);
+ igt_assert((i + 2 + len) <= max_words);
+
+ igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
+
+ value = data[i + 2];
+ switch (data[i]) {
+ case INTEL_HWCONFIG_MEMORY_TYPE:
+ igt_assert(len == 1);
+ switch (value) {
+ case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
+ igt_info("LPDDR4\n");
+ break;
+ case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
+ igt_info("LPDDR5\n");
+ break;
+ default:
+ igt_assert(0);
+ }
+ break;
+
+ case INTEL_HWCONFIG_CACHE_TYPES:
+ igt_assert(len == 1);
+
+#define TEST_CACHE_TYPE(type) \
+ if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
+ value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
+ igt_info(#type); \
+ if (value) \
+ igt_info(", "); \
+ }
+
+ TEST_CACHE_TYPE(L3);
+ TEST_CACHE_TYPE(LLC);
+ TEST_CACHE_TYPE(EDRAM);
+#undef TEST_CACHE_TYPE
+
+ igt_assert(value == 0);
+ igt_info("\n");
+ break;
+
+ default:
+ for (j = i + 2; j < i + 1 + len; j++)
+ igt_info("%d, ", data[j]);
+ igt_info("%d\n", data[j]);
+ }
+
+ /* Advance to next key */
+ i += 2 + len;
+ }
+
+ free(data);
+}
+
igt_main
{
int fd = -1;
@@ -911,6 +1076,9 @@ igt_main
engines(fd);
}
+ igt_subtest("hwconfig_table")
+ query_parse_and_validate_hwconfig_table(fd);
+
igt_fixture {
close(fd);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [igt-dev] ✗ Fi.CI.BAT: failure for Add test for new hw info query
2021-09-15 21:55 [Intel-gfx] [PATCH i-g-t 0/1] Add test for new hw info query John.C.Harrison
2021-09-15 21:55 ` [igt-dev] " John.C.Harrison
@ 2021-09-15 22:26 ` Patchwork
1 sibling, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-09-15 22:26 UTC (permalink / raw)
To: john.c.harrison; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 6539 bytes --]
== Series Details ==
Series: Add test for new hw info query
URL : https://patchwork.freedesktop.org/series/94715/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10594 -> IGTPW_6222
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_6222 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_6222, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_6222:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload:
- fi-kbl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-kbl-guc/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-kbl-guc/igt@i915_module_load@reload.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][3] -> [FAIL][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
Known issues
------------
Here are the changes found in IGTPW_6222 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-cfl-guc: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-cfl-guc/igt@amdgpu/amd_basic@cs-compute.html
- fi-skl-guc: NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-skl-guc/igt@amdgpu/amd_basic@cs-compute.html
* igt@amdgpu/amd_basic@cs-gfx:
- fi-rkl-guc: NOTRUN -> [SKIP][7] ([fdo#109315]) +17 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-cfl-8109u/igt@amdgpu/amd_basic@cs-sdma.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109315]) +17 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@i915_module_load@reload:
- fi-cfl-8109u: NOTRUN -> [DMESG-WARN][10] ([i915#4136])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-cfl-8109u/igt@i915_module_load@reload.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#2868])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] ([i915#295]) +18 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-rkl-guc: [INCOMPLETE][15] ([i915#4130]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-guc: [INCOMPLETE][17] ([i915#4130]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-icl-u2: [INCOMPLETE][19] ([i915#4130]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8109u: [INCOMPLETE][21] ([i915#4130]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
- fi-skl-guc: [INCOMPLETE][23] ([i915#4130]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10594/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
[i915#4136]: https://gitlab.freedesktop.org/drm/intel/issues/4136
Participating hosts (39 -> 35)
------------------------------
Missing (4): fi-bdw-samus fi-rkl-11600 bat-dg1-6 fi-tgl-1115g4
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6209 -> IGTPW_6222
CI-20190529: 20190529
CI_DRM_10594: b615e30a53680656e5b1f7670b34b1cac2a6be27 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_6222: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/index.html
IGT_6209: 07d6594ed02f55b68d64fa6dd7f80cfbc1ce4ef8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
== Testlist changes ==
+igt@i915_query@hwconfig_table
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6222/index.html
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
2021-09-15 21:55 ` [igt-dev] " John.C.Harrison
@ 2021-09-16 8:59 ` Petri Latvala
-1 siblings, 0 replies; 11+ messages in thread
From: Petri Latvala @ 2021-09-16 8:59 UTC (permalink / raw)
To: John.C.Harrison
Cc: IGT-Dev, Intel-GFX, Rodrigo Vivi, Slawomir Milczarek, Matthew Brost
On Wed, Sep 15, 2021 at 02:55:58PM -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the existing query API. So add a test for it as both an
> example of how to fetch the table and to validate the contents as much
> as is possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
> tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 275 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index b9632bb2c..ae0c8dfad 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_ENGINE_INFO 2
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> /* Must be kept compact -- no holes and well documented */
Please update i915_drm.h with a copy from the kernel and state in the
commit message which kernel commit sha it's from. If this change is
not in the kernel yet, add this token to lib/i915/i915_drm_local.h
instead.
--
Petri Latvala
>
> /**
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000..c9961e6bd
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,106 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + __INTEL_HWCONFIG_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> +};
> +
> +enum {
> + INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
> + INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
> + INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
> +};
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 3c791b8ba..1802287e3 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -842,6 +843,170 @@ static void engines(int fd)
> free(engines);
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
> + };
> + uint32_t *data, value;
> + int i = 0;
> + int len, j, max_words, table_size;
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + table_size = item.length;
> + igt_require(table_size > 0);
> +
> + data = malloc(table_size);
> + igt_assert(data);
> + memset(data, 0, table_size);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_assert(item.length == table_size);
> + igt_info("Table size = %d bytes\n", table_size);
> + igt_assert(table_size > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = table_size / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == table_size);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
> +
> + len = data[i + 1];
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
> +
> + value = data[i + 2];
> + switch (data[i]) {
> + case INTEL_HWCONFIG_MEMORY_TYPE:
> + igt_assert(len == 1);
> + switch (value) {
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
> + igt_info("LPDDR4\n");
> + break;
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
> + igt_info("LPDDR5\n");
> + break;
> + default:
> + igt_assert(0);
> + }
> + break;
> +
> + case INTEL_HWCONFIG_CACHE_TYPES:
> + igt_assert(len == 1);
> +
> +#define TEST_CACHE_TYPE(type) \
> + if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
> + value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
> + igt_info(#type); \
> + if (value) \
> + igt_info(", "); \
> + }
> +
> + TEST_CACHE_TYPE(L3);
> + TEST_CACHE_TYPE(LLC);
> + TEST_CACHE_TYPE(EDRAM);
> +#undef TEST_CACHE_TYPE
> +
> + igt_assert(value == 0);
> + igt_info("\n");
> + break;
> +
> + default:
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info("%d, ", data[j]);
> + igt_info("%d\n", data[j]);
> + }
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -911,6 +1076,9 @@ igt_main
> engines(fd);
> }
>
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
@ 2021-09-16 8:59 ` Petri Latvala
0 siblings, 0 replies; 11+ messages in thread
From: Petri Latvala @ 2021-09-16 8:59 UTC (permalink / raw)
To: John.C.Harrison
Cc: IGT-Dev, Intel-GFX, Rodrigo Vivi, Slawomir Milczarek, Matthew Brost
On Wed, Sep 15, 2021 at 02:55:58PM -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the existing query API. So add a test for it as both an
> example of how to fetch the table and to validate the contents as much
> as is possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
> tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 275 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index b9632bb2c..ae0c8dfad 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_ENGINE_INFO 2
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> /* Must be kept compact -- no holes and well documented */
Please update i915_drm.h with a copy from the kernel and state in the
commit message which kernel commit sha it's from. If this change is
not in the kernel yet, add this token to lib/i915/i915_drm_local.h
instead.
--
Petri Latvala
>
> /**
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000..c9961e6bd
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,106 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + __INTEL_HWCONFIG_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> +};
> +
> +enum {
> + INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
> + INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
> + INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
> +};
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 3c791b8ba..1802287e3 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -842,6 +843,170 @@ static void engines(int fd)
> free(engines);
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
> + };
> + uint32_t *data, value;
> + int i = 0;
> + int len, j, max_words, table_size;
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + table_size = item.length;
> + igt_require(table_size > 0);
> +
> + data = malloc(table_size);
> + igt_assert(data);
> + memset(data, 0, table_size);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_assert(item.length == table_size);
> + igt_info("Table size = %d bytes\n", table_size);
> + igt_assert(table_size > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = table_size / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == table_size);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
> +
> + len = data[i + 1];
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
> +
> + value = data[i + 2];
> + switch (data[i]) {
> + case INTEL_HWCONFIG_MEMORY_TYPE:
> + igt_assert(len == 1);
> + switch (value) {
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
> + igt_info("LPDDR4\n");
> + break;
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
> + igt_info("LPDDR5\n");
> + break;
> + default:
> + igt_assert(0);
> + }
> + break;
> +
> + case INTEL_HWCONFIG_CACHE_TYPES:
> + igt_assert(len == 1);
> +
> +#define TEST_CACHE_TYPE(type) \
> + if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
> + value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
> + igt_info(#type); \
> + if (value) \
> + igt_info(", "); \
> + }
> +
> + TEST_CACHE_TYPE(L3);
> + TEST_CACHE_TYPE(LLC);
> + TEST_CACHE_TYPE(EDRAM);
> +#undef TEST_CACHE_TYPE
> +
> + igt_assert(value == 0);
> + igt_info("\n");
> + break;
> +
> + default:
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info("%d, ", data[j]);
> + igt_info("%d\n", data[j]);
> + }
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -911,6 +1076,9 @@ igt_main
> engines(fd);
> }
>
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
2021-09-16 8:59 ` Petri Latvala
@ 2021-09-16 17:27 ` John Harrison
-1 siblings, 0 replies; 11+ messages in thread
From: John Harrison @ 2021-09-16 17:27 UTC (permalink / raw)
To: Petri Latvala
Cc: IGT-Dev, Intel-GFX, Rodrigo Vivi, Slawomir Milczarek, Matthew Brost
On 9/16/2021 01:59, Petri Latvala wrote:
> On Wed, Sep 15, 2021 at 02:55:58PM -0700, John.C.Harrison@Intel.com wrote:
>> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> Newer platforms have an embedded table giving details about that
>> platform's hardware configuration. This table can be retrieved from
>> the KMD via the existing query API. So add a test for it as both an
>> example of how to fetch the table and to validate the contents as much
>> as is possible.
>>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
>> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
>> ---
>> include/drm-uapi/i915_drm.h | 1 +
>> lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
>> tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
>> 3 files changed, 275 insertions(+)
>> create mode 100644 lib/intel_hwconfig_types.h
>>
>> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
>> index b9632bb2c..ae0c8dfad 100644
>> --- a/include/drm-uapi/i915_drm.h
>> +++ b/include/drm-uapi/i915_drm.h
>> @@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
>> #define DRM_I915_QUERY_ENGINE_INFO 2
>> #define DRM_I915_QUERY_PERF_CONFIG 3
>> #define DRM_I915_QUERY_MEMORY_REGIONS 4
>> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
>> /* Must be kept compact -- no holes and well documented */
> Please update i915_drm.h with a copy from the kernel and state in the
> commit message which kernel commit sha it's from. If this change is
> not in the kernel yet, add this token to lib/i915/i915_drm_local.h
> instead.
>
>
Neither side is merged yet. My understanding is that all sides need to
be posted in parallel for CI to work. Once green and reviewed, the
kernel side gets merged first. Then the IGT/UMD patches get updated with
the official kernel headers, reposted and then merged.
John.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
@ 2021-09-16 17:27 ` John Harrison
0 siblings, 0 replies; 11+ messages in thread
From: John Harrison @ 2021-09-16 17:27 UTC (permalink / raw)
To: Petri Latvala
Cc: IGT-Dev, Intel-GFX, Rodrigo Vivi, Slawomir Milczarek, Matthew Brost
On 9/16/2021 01:59, Petri Latvala wrote:
> On Wed, Sep 15, 2021 at 02:55:58PM -0700, John.C.Harrison@Intel.com wrote:
>> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>
>> Newer platforms have an embedded table giving details about that
>> platform's hardware configuration. This table can be retrieved from
>> the KMD via the existing query API. So add a test for it as both an
>> example of how to fetch the table and to validate the contents as much
>> as is possible.
>>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
>> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
>> ---
>> include/drm-uapi/i915_drm.h | 1 +
>> lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
>> tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
>> 3 files changed, 275 insertions(+)
>> create mode 100644 lib/intel_hwconfig_types.h
>>
>> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
>> index b9632bb2c..ae0c8dfad 100644
>> --- a/include/drm-uapi/i915_drm.h
>> +++ b/include/drm-uapi/i915_drm.h
>> @@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
>> #define DRM_I915_QUERY_ENGINE_INFO 2
>> #define DRM_I915_QUERY_PERF_CONFIG 3
>> #define DRM_I915_QUERY_MEMORY_REGIONS 4
>> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
>> /* Must be kept compact -- no holes and well documented */
> Please update i915_drm.h with a copy from the kernel and state in the
> commit message which kernel commit sha it's from. If this change is
> not in the kernel yet, add this token to lib/i915/i915_drm_local.h
> instead.
>
>
Neither side is merged yet. My understanding is that all sides need to
be posted in parallel for CI to work. Once green and reviewed, the
kernel side gets merged first. Then the IGT/UMD patches get updated with
the official kernel headers, reposted and then merged.
John.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
2021-09-16 17:27 ` John Harrison
@ 2021-09-17 8:37 ` Petri Latvala
-1 siblings, 0 replies; 11+ messages in thread
From: Petri Latvala @ 2021-09-17 8:37 UTC (permalink / raw)
To: John Harrison
Cc: IGT-Dev, Intel-GFX, Rodrigo Vivi, Slawomir Milczarek, Matthew Brost
On Thu, Sep 16, 2021 at 10:27:41AM -0700, John Harrison wrote:
> On 9/16/2021 01:59, Petri Latvala wrote:
> > On Wed, Sep 15, 2021 at 02:55:58PM -0700, John.C.Harrison@Intel.com wrote:
> > > From: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > >
> > > Newer platforms have an embedded table giving details about that
> > > platform's hardware configuration. This table can be retrieved from
> > > the KMD via the existing query API. So add a test for it as both an
> > > example of how to fetch the table and to validate the contents as much
> > > as is possible.
> > >
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> > > Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > > include/drm-uapi/i915_drm.h | 1 +
> > > lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
> > > tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
> > > 3 files changed, 275 insertions(+)
> > > create mode 100644 lib/intel_hwconfig_types.h
> > >
> > > diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> > > index b9632bb2c..ae0c8dfad 100644
> > > --- a/include/drm-uapi/i915_drm.h
> > > +++ b/include/drm-uapi/i915_drm.h
> > > @@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
> > > #define DRM_I915_QUERY_ENGINE_INFO 2
> > > #define DRM_I915_QUERY_PERF_CONFIG 3
> > > #define DRM_I915_QUERY_MEMORY_REGIONS 4
> > > +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> > > /* Must be kept compact -- no holes and well documented */
> > Please update i915_drm.h with a copy from the kernel and state in the
> > commit message which kernel commit sha it's from. If this change is
> > not in the kernel yet, add this token to lib/i915/i915_drm_local.h
> > instead.
> >
> >
> Neither side is merged yet. My understanding is that all sides need to be
> posted in parallel for CI to work. Once green and reviewed, the kernel side
> gets merged first. Then the IGT/UMD patches get updated with the official
> kernel headers, reposted and then merged.
That lockstep dancing removal is the point of i915_drm_local.h. IGT
side can even be merged that way before kernel side is ready, then
updated with the real thing later at whatever cadence.
--
Petri Latvala
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
@ 2021-09-17 8:37 ` Petri Latvala
0 siblings, 0 replies; 11+ messages in thread
From: Petri Latvala @ 2021-09-17 8:37 UTC (permalink / raw)
To: John Harrison
Cc: IGT-Dev, Intel-GFX, Rodrigo Vivi, Slawomir Milczarek, Matthew Brost
On Thu, Sep 16, 2021 at 10:27:41AM -0700, John Harrison wrote:
> On 9/16/2021 01:59, Petri Latvala wrote:
> > On Wed, Sep 15, 2021 at 02:55:58PM -0700, John.C.Harrison@Intel.com wrote:
> > > From: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > >
> > > Newer platforms have an embedded table giving details about that
> > > platform's hardware configuration. This table can be retrieved from
> > > the KMD via the existing query API. So add a test for it as both an
> > > example of how to fetch the table and to validate the contents as much
> > > as is possible.
> > >
> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > > Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> > > Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > > include/drm-uapi/i915_drm.h | 1 +
> > > lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
> > > tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
> > > 3 files changed, 275 insertions(+)
> > > create mode 100644 lib/intel_hwconfig_types.h
> > >
> > > diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> > > index b9632bb2c..ae0c8dfad 100644
> > > --- a/include/drm-uapi/i915_drm.h
> > > +++ b/include/drm-uapi/i915_drm.h
> > > @@ -2451,6 +2451,7 @@ struct drm_i915_query_item {
> > > #define DRM_I915_QUERY_ENGINE_INFO 2
> > > #define DRM_I915_QUERY_PERF_CONFIG 3
> > > #define DRM_I915_QUERY_MEMORY_REGIONS 4
> > > +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> > > /* Must be kept compact -- no holes and well documented */
> > Please update i915_drm.h with a copy from the kernel and state in the
> > commit message which kernel commit sha it's from. If this change is
> > not in the kernel yet, add this token to lib/i915/i915_drm_local.h
> > instead.
> >
> >
> Neither side is merged yet. My understanding is that all sides need to be
> posted in parallel for CI to work. Once green and reviewed, the kernel side
> gets merged first. Then the IGT/UMD patches get updated with the official
> kernel headers, reposted and then merged.
That lockstep dancing removal is the point of i915_drm_local.h. IGT
side can even be merged that way before kernel side is ready, then
updated with the real thing later at whatever cadence.
--
Petri Latvala
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table
2021-07-27 0:28 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
@ 2021-09-15 3:47 ` Matthew Brost
0 siblings, 0 replies; 11+ messages in thread
From: Matthew Brost @ 2021-09-15 3:47 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
On Mon, Jul 26, 2021 at 05:28:12PM -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the query API. So add a test for it as both an example of
> how to fetch the table and to validate the contents as much as
> possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> ---
> include/drm-uapi/i915_drm.h | 1 +
> lib/intel_hwconfig_types.h | 106 +++++++++++++++++++++++
> tests/i915/i915_query.c | 168 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 275 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index a1c0030c3..5c34ab759 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -2233,6 +2233,7 @@ struct drm_i915_query_item {
> #define DRM_I915_QUERY_ENGINE_INFO 2
> #define DRM_I915_QUERY_PERF_CONFIG 3
> #define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_TABLE 5
> /* Must be kept compact -- no holes and well documented */
>
> /**
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000..c9961e6bd
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,106 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + __INTEL_HWCONFIG_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> +};
> +
> +enum {
> + INTEL_HWCONFIG_CACHE_TYPE_L3 = BIT(0),
> + INTEL_HWCONFIG_CACHE_TYPE_LLC = BIT(1),
> + INTEL_HWCONFIG_CACHE_TYPE_EDRAM = BIT(2),
> +};
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 3c791b8ba..1802287e3 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -842,6 +843,170 @@ static void engines(int fd)
> free(engines);
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_TABLE,
> + };
> + uint32_t *data, value;
> + int i = 0;
> + int len, j, max_words, table_size;
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + table_size = item.length;
> + igt_require(table_size > 0);
> +
> + data = malloc(table_size);
> + igt_assert(data);
> + memset(data, 0, table_size);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_assert(item.length == table_size);
> + igt_info("Table size = %d bytes\n", table_size);
> + igt_assert(table_size > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = table_size / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == table_size);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_LIMIT);
> +
> + len = data[i + 1];
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
> +
> + value = data[i + 2];
> + switch (data[i]) {
> + case INTEL_HWCONFIG_MEMORY_TYPE:
> + igt_assert(len == 1);
> + switch (value) {
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4:
> + igt_info("LPDDR4\n");
> + break;
> + case INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5:
> + igt_info("LPDDR5\n");
> + break;
> + default:
> + igt_assert(0);
> + }
> + break;
> +
> + case INTEL_HWCONFIG_CACHE_TYPES:
> + igt_assert(len == 1);
> +
> +#define TEST_CACHE_TYPE(type) \
> + if (value & INTEL_HWCONFIG_CACHE_TYPE_##type) { \
> + value &= ~INTEL_HWCONFIG_CACHE_TYPE_##type; \
> + igt_info(#type); \
> + if (value) \
> + igt_info(", "); \
> + }
> +
> + TEST_CACHE_TYPE(L3);
> + TEST_CACHE_TYPE(LLC);
> + TEST_CACHE_TYPE(EDRAM);
> +#undef TEST_CACHE_TYPE
> +
> + igt_assert(value == 0);
> + igt_info("\n");
> + break;
> +
> + default:
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info("%d, ", data[j]);
> + igt_info("%d\n", data[j]);
> + }
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -911,6 +1076,9 @@ igt_main
> engines(fd);
> }
>
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.25.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-09-17 8:37 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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2021-09-15 21:55 [Intel-gfx] [PATCH i-g-t 0/1] Add test for new hw info query John.C.Harrison
2021-09-15 21:55 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2021-09-15 21:55 ` [igt-dev] " John.C.Harrison
2021-09-16 8:59 ` [Intel-gfx] " Petri Latvala
2021-09-16 8:59 ` Petri Latvala
2021-09-16 17:27 ` [Intel-gfx] " John Harrison
2021-09-16 17:27 ` John Harrison
2021-09-17 8:37 ` Petri Latvala
2021-09-17 8:37 ` Petri Latvala
2021-09-15 22:26 ` [igt-dev] ✗ Fi.CI.BAT: failure for Add test for new hw info query Patchwork
-- strict thread matches above, loose matches on Subject: below --
2021-07-27 0:28 [Intel-gfx] [PATCH i-g-t 0/1] Add tests " John.C.Harrison
2021-07-27 0:28 ` [Intel-gfx] [PATCH i-g-t 1/1] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2021-09-15 3:47 ` [Intel-gfx] [igt-dev] " Matthew Brost
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