From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC3B1C433EF for ; Fri, 17 Sep 2021 12:32:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2EDC611C4 for ; Fri, 17 Sep 2021 12:32:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A2EDC611C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2804E89DBC; Fri, 17 Sep 2021 12:32:55 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5EBB389DBC for ; Fri, 17 Sep 2021 12:32:54 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="308334214" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="308334214" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 05:32:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="509902528" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga008.fm.intel.com with SMTP; 17 Sep 2021 05:32:51 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 17 Sep 2021 15:32:51 +0300 Date: Fri, 17 Sep 2021 15:32:51 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: "Lisovskiy, Stanislav" Cc: intel-gfx@lists.freedesktop.org Message-ID: References: <20210514125751.17075-1-ville.syrjala@linux.intel.com> <20210514125751.17075-3-ville.syrjala@linux.intel.com> <20210916162421.GB30274@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210916162421.GB30274@intel.com> X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH 02/14] drm/i915: Fix g4x cxsr enable condition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Sep 16, 2021 at 07:24:21PM +0300, Lisovskiy, Stanislav wrote: > On Fri, May 14, 2021 at 03:57:39PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > The intention was to check whether the primary plane is enabled > > without any sprites planes being enabled. Instead we ended up checking > > whether just any one of the planes is enabled. g4x isn't vlv/chv and > > cxsr only works with the primary plane. Fix the check to examine the > > bitmask of active planes rather than the number of bits set in said > > bitmask. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_pm.c | 5 ++--- > > 1 file changed, 2 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 00a5fe424c5a..2fb496fbed43 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -1376,8 +1376,7 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > > struct intel_atomic_state *state = > > to_intel_atomic_state(crtc_state->uapi.state); > > struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; > > - int num_active_planes = hweight8(crtc_state->active_planes & > > - ~BIT(PLANE_CURSOR)); > > + u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); > > const struct g4x_pipe_wm *raw; > > const struct intel_plane_state *old_plane_state; > > const struct intel_plane_state *new_plane_state; > > @@ -1417,7 +1416,7 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) > > wm_state->sr.cursor = raw->plane[PLANE_CURSOR]; > > wm_state->sr.fbc = raw->fbc; > > > > - wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); > > + wm_state->cxsr = active_planes == BIT(PLANE_PRIMARY); > > Shouldn't this be "active_planes & BIT(PLANE_PRIMARY)" as we might > have other non-cursor planes enabled, which will then fail or am I missing something? CxSR is possible only when the primary plane is enabled and the sprite plane is disabled. -- Ville Syrjälä Intel