From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11EBFC433F5 for ; Mon, 20 Sep 2021 15:31:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA4C4610FB for ; Mon, 20 Sep 2021 15:31:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241697AbhITPdY (ORCPT ); Mon, 20 Sep 2021 11:33:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:57384 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241644AbhITPdT (ORCPT ); Mon, 20 Sep 2021 11:33:19 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 86DD66115C; Mon, 20 Sep 2021 15:31:50 +0000 (UTC) Date: Mon, 20 Sep 2021 16:31:47 +0100 From: Catalin Marinas To: Vincenzo Frascino Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, Andrew Morton , Will Deacon , Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Branislav Rankov , Andrey Konovalov , Lorenzo Pieralisi Subject: Re: [PATCH 4/5] arm64: mte: Add asymmetric mode support Message-ID: References: <20210913081424.48613-1-vincenzo.frascino@arm.com> <20210913081424.48613-5-vincenzo.frascino@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210913081424.48613-5-vincenzo.frascino@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Sep 13, 2021 at 09:14:23AM +0100, Vincenzo Frascino wrote: > MTE provides an asymmetric mode for detecting tag exceptions. In > particular, when such a mode is present, the CPU triggers a fault > on a tag mismatch during a load operation and asynchronously updates > a register when a tag mismatch is detected during a store operation. > > Add support for MTE asymmetric mode. > > Note: If the CPU does not support MTE asymmetric mode the kernel falls > back on synchronous mode which is the default for kasan=on. > > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Andrey Konovalov > Signed-off-by: Vincenzo Frascino Reviewed-by: Catalin Marinas From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E7C6C433F5 for ; Mon, 20 Sep 2021 15:33:56 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2818260F58 for ; Mon, 20 Sep 2021 15:33:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2818260F58 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OU15eSj1fqz9WUded12MShjK5282+0PIFATZQa3ZiRY=; b=uo8Pg9lREMHyKY Z+R2/sffZ8ZRMeAmrM+fheow/dhsnEEwWuwMVwDcczC2tDRjgxi+pPoO6TzoXtWNCPgMSiLgkA/xl 0GKVODd4qG9E/TCltandiDmxKHU0993RH2vp+ICk1yok1Y8wurN8bGh+4kEdTsQbAfNsoWKc7ehE8 QbZstok7hb2u6rfUdTZajHESlSr+MSU2nLvETKLjKTiGEzwvJlBAMnh2w20zX6nCA053TeRzKjEGB 22A+STBQeeXFJHIfuWyKMvBnV/9+tzA9jz07sxBKBKMioRkA86l/r31R30VJx1+1vPiqBsxSLBcTe l14bE4bZ9NIRR6t0DFdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSLH7-002DnT-7c; Mon, 20 Sep 2021 15:32:09 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mSLGr-002DhX-0Z for linux-arm-kernel@lists.infradead.org; Mon, 20 Sep 2021 15:31:54 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 86DD66115C; Mon, 20 Sep 2021 15:31:50 +0000 (UTC) Date: Mon, 20 Sep 2021 16:31:47 +0100 From: Catalin Marinas To: Vincenzo Frascino Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, Andrew Morton , Will Deacon , Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Branislav Rankov , Andrey Konovalov , Lorenzo Pieralisi Subject: Re: [PATCH 4/5] arm64: mte: Add asymmetric mode support Message-ID: References: <20210913081424.48613-1-vincenzo.frascino@arm.com> <20210913081424.48613-5-vincenzo.frascino@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210913081424.48613-5-vincenzo.frascino@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210920_083153_145402_5154D130 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Sep 13, 2021 at 09:14:23AM +0100, Vincenzo Frascino wrote: > MTE provides an asymmetric mode for detecting tag exceptions. In > particular, when such a mode is present, the CPU triggers a fault > on a tag mismatch during a load operation and asynchronously updates > a register when a tag mismatch is detected during a store operation. > > Add support for MTE asymmetric mode. > > Note: If the CPU does not support MTE asymmetric mode the kernel falls > back on synchronous mode which is the default for kasan=on. > > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Andrey Konovalov > Signed-off-by: Vincenzo Frascino Reviewed-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel