From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB446C433F5 for ; Thu, 7 Oct 2021 16:10:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 89B9C6103C for ; Thu, 7 Oct 2021 16:10:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233448AbhJGQMR (ORCPT ); Thu, 7 Oct 2021 12:12:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:59790 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232589AbhJGQMQ (ORCPT ); Thu, 7 Oct 2021 12:12:16 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6CB9D61074; Thu, 7 Oct 2021 16:10:20 +0000 (UTC) Date: Thu, 7 Oct 2021 17:10:18 +0100 From: Catalin Marinas To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, mark.rutland@arm.com, james.morse@arm.com, anshuman.khandual@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org Subject: Re: [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Message-ID: References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-12-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210921134121.2423546-12-suzuki.poulose@arm.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 21, 2021 at 02:41:15PM +0100, Suzuki K Poulose wrote: > Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers > from errata, where a TSB (trace synchronization barrier) > fails to flush the trace data completely, when executed from > a trace prohibited region. In Linux we always execute it > after we have moved the PE to trace prohibited region. So, > we can apply the workaround everytime a TSB is executed. > > The work around is to issue two TSB consecutively. > > NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying > that a late CPU could be blocked from booting if it is the > first CPU that requires the workaround. This is because we > do not allow setting a cpu_hwcaps after the SMP boot. The > other alternative is to use "this_cpu_has_cap()" instead > of the faster system wide check, which may be a bit of an > overhead, given we may have to do this in nvhe KVM host > before a guest entry. > > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Mark Rutland > Cc: Anshuman Khandual > Cc: Marc Zyngier > Signed-off-by: Suzuki K Poulose Acked-by: Catalin Marinas From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A63D3C433EF for ; Thu, 7 Oct 2021 16:12:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CEDC61074 for ; Thu, 7 Oct 2021 16:12:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6CEDC61074 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=G3ryfQOKJ37GPogPEt4rViJqiWk+CI/EzOlZG1o0r58=; b=CPq2AIjszy3RWY F1kvBaEcxmp2ivPik6/I9qzvnbh9rHgZNJ166v3k+v5Cl3dYiejk41CnYzz+JGBF//DcEl3IsdUI/ G3B9B1Dzdha+KeWyZaTJ29dovOymakmj1GWV6lXq0u4TYrKdlIFFyQukHpGojgb9E2Wtn8eUcvOqN V6RsAggCTUiY4Hz7TE+c5DXxUX7viB2sFGR83BxLjFHin5pg7FJ1rVzZN7aATTRrRVIF7WjEN6K5J 6WLqVqvbawaSPyZAuNpPQNK/W+8+XKLWXUSWw3yj7JRJ1Z7cT2kcNNSrrjQfo5CDSaStfijO+7iuK pzsFGQlJEeNhZZlqRP5g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYVyU-000EFL-Hy; Thu, 07 Oct 2021 16:10:26 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYVyQ-000EEX-Qv for linux-arm-kernel@lists.infradead.org; Thu, 07 Oct 2021 16:10:24 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 6CB9D61074; Thu, 7 Oct 2021 16:10:20 +0000 (UTC) Date: Thu, 7 Oct 2021 17:10:18 +0100 From: Catalin Marinas To: Suzuki K Poulose Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maz@kernel.org, mark.rutland@arm.com, james.morse@arm.com, anshuman.khandual@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org Subject: Re: [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Message-ID: References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-12-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210921134121.2423546-12-suzuki.poulose@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211007_091022_920090_B8DDF88F X-CRM114-Status: GOOD ( 14.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 21, 2021 at 02:41:15PM +0100, Suzuki K Poulose wrote: > Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers > from errata, where a TSB (trace synchronization barrier) > fails to flush the trace data completely, when executed from > a trace prohibited region. In Linux we always execute it > after we have moved the PE to trace prohibited region. So, > we can apply the workaround everytime a TSB is executed. > > The work around is to issue two TSB consecutively. > > NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying > that a late CPU could be blocked from booting if it is the > first CPU that requires the workaround. This is because we > do not allow setting a cpu_hwcaps after the SMP boot. The > other alternative is to use "this_cpu_has_cap()" instead > of the faster system wide check, which may be a bit of an > overhead, given we may have to do this in nvhe KVM host > before a guest entry. > > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Mathieu Poirier > Cc: Mike Leach > Cc: Mark Rutland > Cc: Anshuman Khandual > Cc: Marc Zyngier > Signed-off-by: Suzuki K Poulose Acked-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel