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From: Greg KH <gregkh@linuxfoundation.org>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: lee.jones@linaro.org, bhelgaas@google.com,
	andy.shevchenko@gmail.com, mgross@linux.intel.com,
	srinivas.pandruvada@intel.com, linux-kernel@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 2/5] MFD: intel_pmt: Support non-PMT capabilities
Date: Tue, 28 Sep 2021 07:01:09 +0200	[thread overview]
Message-ID: <YVKhlWSb3pdMLCEk@kroah.com> (raw)
In-Reply-To: <d540894d3d8c05722bd924c21bd9dd9c2b9def53.camel@linux.intel.com>

On Mon, Sep 27, 2021 at 11:40:37AM -0700, David E. Box wrote:
> On Mon, 2021-09-27 at 19:36 +0200, Greg KH wrote:
> > On Wed, Sep 22, 2021 at 02:30:04PM -0700, David E. Box wrote:
> > > Intel Platform Monitoring Technology (PMT) support is indicated by presence
> > > of an Intel defined PCIe DVSEC structure with a PMT ID. However DVSEC
> > > structures may also be used by Intel to indicate support for other
> > > capabilities unrelated to PMT.  OOBMSM is a device that can have both PMT
> > > and non-PMT capabilities. In order to support these capabilities it is
> > > necessary to modify the intel_pmt driver to handle the creation of platform
> > > devices more generically.
> > 
> > I said this on your other driver submission, but why are you turning a
> > PCIe device into a set of platform devices and craming it into the MFD
> > subsystem?
> > 
> > PCIe devices are NOT platform devices.
> 
> But they *are* used to create platform devices when the PCIe device is multi-functional, which is
> what intel_pmt is.

That is an abuse of platform devices, as that is not what they are for.

> > Why not use the auxiliary bus for this thing if you have individual
> > drivers that need to "bind" to the different attributes that this single
> > PCIe device is exporting.
> 
> It wasn't clear in the beginning how this would evolve. MFD made sense for the PMT (platform
> monitoring technology) driver. PMT has 3 related but individually enumerable devices on the same IP,
> like lpss. But the same IP is now being used for other features too like SDSi. We could work on
> converting this to the auxiliary bus and then covert the cell drivers.

Please do so.

> > Or why not just fix the hardware to report individual PCIe devices, like
> > a sane system would do?
> 
> We have some systems with 1000+ PCIe devices. Each PCIe device adds cost to HW. So increasingly
> VSEC/DVSEC is used to expose features which are handled by the same micro-controller in the HW.

A PCIe device is a virtual thing, what HW cost do they have?

Anyway, a platform device should NOT ever be a child of a PCI device,
that is not ok and should be fixed here please.

A platform device is just that, something that the platform provides on
a non-discoverable bus.  A PCIe device is NOT that type of device at
all and never has been.

thanks,

greg k-h

  reply	other threads:[~2021-09-28  5:01 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-22 21:30 [PATCH v3 0/5] Add general DVSEC/VSEC support David E. Box
2021-09-22 21:30 ` [PATCH v3 1/5] PCI: Add #defines for accessing PCIE DVSEC fields David E. Box
2021-09-27 17:30   ` Bjorn Helgaas
2021-09-22 21:30 ` [PATCH v3 2/5] MFD: intel_pmt: Support non-PMT capabilities David E. Box
2021-09-27 17:36   ` Greg KH
2021-09-27 18:40     ` David E. Box
2021-09-28  5:01       ` Greg KH [this message]
2021-09-28  7:54       ` Lee Jones
2021-09-28  9:10         ` Greg KH
2021-09-28 10:03           ` Lee Jones
2021-09-22 21:30 ` [PATCH v3 3/5] MFD: intel_pmt: Add support for PCIe VSEC structures David E. Box
2021-09-22 21:30 ` [PATCH v3 4/5] MFD: intel_pmt: Add DG2 support David E. Box
2021-09-22 21:30 ` [PATCH v3 5/5] MFD: intel_extended_cap: Add support for Intel SDSi David E. Box
2021-09-23  9:04 ` [PATCH v3 0/5] Add general DVSEC/VSEC support Hans de Goede
2021-09-23 15:44   ` David E. Box

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