From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8256EC433F5 for ; Wed, 29 Sep 2021 00:08:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B6DD613D1 for ; Wed, 29 Sep 2021 00:08:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243390AbhI2AJp (ORCPT ); Tue, 28 Sep 2021 20:09:45 -0400 Received: from mga03.intel.com ([134.134.136.65]:35948 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243331AbhI2AJn (ORCPT ); Tue, 28 Sep 2021 20:09:43 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10121"; a="224899512" X-IronPort-AV: E=Sophos;i="5.85,330,1624345200"; d="scan'208";a="224899512" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 17:08:02 -0700 X-IronPort-AV: E=Sophos;i="5.85,330,1624345200"; d="scan'208";a="486731358" Received: from agluck-desk2.sc.intel.com (HELO agluck-desk2.amr.corp.intel.com) ([10.3.52.146]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 17:08:02 -0700 Date: Tue, 28 Sep 2021 17:08:00 -0700 From: "Luck, Tony" To: Fenghua Yu Cc: Dave Hansen , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "Peter Zijlstra (Intel)" , Lu Baolu , Joerg Roedel , Josh Poimboeuf , Dave Jiang , Jacob Jun Pan , Raj Ashok , "Shankar, Ravi V" , iommu@lists.linux-foundation.org, the arch/x86 maintainers , Linux Kernel Mailing List Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Message-ID: References: <20210920192349.2602141-5-fenghua.yu@intel.com> <1aae375d-3cd4-4ab8-9c64-9e387916e6c0@www.fastmail.com> <035290e6-d914-a113-ea6c-e845d71069cf@intel.com> <3f97b77e-a609-997b-3be7-f44ff7312b0d@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 28, 2021 at 11:50:37PM +0000, Fenghua Yu wrote: > If xfeatures's feature bit is 0, xsaves will not write its init value to the > memory due to init optimization. So the xsaves will do nothing and the > state is not initialized and may have random data. > Setting TIF_NEED_FPU_LOAD cannot guaranteed to execute XRSTORS on exiting > to user. In fpregs_restore_userregs(): > if (!fpregs_state_valid(fpu, cpu)) { > ... > __restore_fpregs_from_fpstate(&fpu->state, mask); > ... > } > > fpregs state should be invalid to get the XRSTROS executed. > > So setting TIF_NEED_FPU_LOAD may get the FPU register unchanged on exiting > to user. Does this help? Changed lines marked with //<<<<< -Tony void *begin_update_one_xsave_feature(struct task_struct *tsk, enum xfeature xfeature, bool full) { struct xregs_state *xsave = &tsk->thread.fpu.state.xsave; struct xregs_state *xinit = &init_fpstate.xsave; u64 fmask = 1ull << xfeature; void *addr; BUG_ON(!(xsave->header.xcomp_bv & fmask)); fpregs_lock(); addr = __raw_xsave_addr(xsave, xfeature); if (full || tsk != current) { memcpy(addr, __raw_xsave_addr(xinit, xfeature), xstate_sizes[xfeature]); goto out; } if (!(xsave->header.xfeatures & fmask)) { xsave->header.xfeatures |= fmask; //<<<<< xsaves(xsave, fmask); } out: xsave->header.xfeatures |= fmask; return addr; } void finish_update_one_xsave_feature(struct task_struct *tsk) { set_ti_thread_flag(task_thread_info(tsk), TIF_NEED_FPU_LOAD); if (tsk == current) //<<<<< __cpu_invalidate_fpregs_state(); //<<<<< fpregs_unlock(); } From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 496ECC433FE for ; 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a="224899513" X-IronPort-AV: E=Sophos;i="5.85,330,1624345200"; d="scan'208";a="224899513" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 17:08:02 -0700 X-IronPort-AV: E=Sophos;i="5.85,330,1624345200"; d="scan'208";a="486731358" Received: from agluck-desk2.sc.intel.com (HELO agluck-desk2.amr.corp.intel.com) ([10.3.52.146]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2021 17:08:02 -0700 Date: Tue, 28 Sep 2021 17:08:00 -0700 From: "Luck, Tony" To: Fenghua Yu Subject: Re: [PATCH 4/8] x86/traps: Demand-populate PASID MSR via #GP Message-ID: References: <20210920192349.2602141-5-fenghua.yu@intel.com> <1aae375d-3cd4-4ab8-9c64-9e387916e6c0@www.fastmail.com> <035290e6-d914-a113-ea6c-e845d71069cf@intel.com> <3f97b77e-a609-997b-3be7-f44ff7312b0d@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: "Shankar, Ravi V" , Dave Jiang , Raj Ashok , "Peter Zijlstra \(Intel\)" , the arch/x86 maintainers , Linux Kernel Mailing List , Dave Hansen , iommu@lists.linux-foundation.org, Ingo Molnar , Borislav Petkov , Jacob Jun Pan , Andy Lutomirski , Josh Poimboeuf , Thomas Gleixner X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Tue, Sep 28, 2021 at 11:50:37PM +0000, Fenghua Yu wrote: > If xfeatures's feature bit is 0, xsaves will not write its init value to the > memory due to init optimization. So the xsaves will do nothing and the > state is not initialized and may have random data. > Setting TIF_NEED_FPU_LOAD cannot guaranteed to execute XRSTORS on exiting > to user. In fpregs_restore_userregs(): > if (!fpregs_state_valid(fpu, cpu)) { > ... > __restore_fpregs_from_fpstate(&fpu->state, mask); > ... > } > > fpregs state should be invalid to get the XRSTROS executed. > > So setting TIF_NEED_FPU_LOAD may get the FPU register unchanged on exiting > to user. Does this help? Changed lines marked with //<<<<< -Tony void *begin_update_one_xsave_feature(struct task_struct *tsk, enum xfeature xfeature, bool full) { struct xregs_state *xsave = &tsk->thread.fpu.state.xsave; struct xregs_state *xinit = &init_fpstate.xsave; u64 fmask = 1ull << xfeature; void *addr; BUG_ON(!(xsave->header.xcomp_bv & fmask)); fpregs_lock(); addr = __raw_xsave_addr(xsave, xfeature); if (full || tsk != current) { memcpy(addr, __raw_xsave_addr(xinit, xfeature), xstate_sizes[xfeature]); goto out; } if (!(xsave->header.xfeatures & fmask)) { xsave->header.xfeatures |= fmask; //<<<<< xsaves(xsave, fmask); } out: xsave->header.xfeatures |= fmask; return addr; } void finish_update_one_xsave_feature(struct task_struct *tsk) { set_ti_thread_flag(task_thread_info(tsk), TIF_NEED_FPU_LOAD); if (tsk == current) //<<<<< __cpu_invalidate_fpregs_state(); //<<<<< fpregs_unlock(); } _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu