From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4764AC433F5 for ; Wed, 29 Sep 2021 18:31:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 302B4613D1 for ; Wed, 29 Sep 2021 18:31:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346212AbhI2SdO (ORCPT ); Wed, 29 Sep 2021 14:33:14 -0400 Received: from mga02.intel.com ([134.134.136.20]:61107 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346190AbhI2SdK (ORCPT ); Wed, 29 Sep 2021 14:33:10 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10122"; a="212267247" X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="212267247" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 11:31:29 -0700 X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="563481249" Received: from agluck-desk2.sc.intel.com (HELO agluck-desk2.amr.corp.intel.com) ([10.3.52.146]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 11:31:28 -0700 Date: Wed, 29 Sep 2021 11:31:27 -0700 From: "Luck, Tony" To: Fenghua Yu Cc: Thomas Gleixner , Andy Lutomirski , Peter Zijlstra , Ingo Molnar , Borislav Petkov , Dave Hansen , Lu Baolu , Joerg Roedel , Josh Poimboeuf , Dave Jiang , Jacob Jun Pan , Raj Ashok , "Shankar, Ravi V" , iommu@lists.linux-foundation.org, the arch/x86 maintainers , Linux Kernel Mailing List Subject: Re: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Message-ID: References: <87o88jfajo.ffs@tglx> <87k0j6dsdn.ffs@tglx> <87r1d78t2e.ffs@tglx> <75e95acc-6730-ddcf-d722-66e575076256@kernel.org> <877dez8fqu.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 29, 2021 at 06:07:22PM +0000, Fenghua Yu wrote: > Add > +#ifdef CONFIG_IOMMU_SUPPORT > because mm->pasid and current-pasid_activated are defined only if > CONFIG_IOMMU_SUPPORT is defined. > > > + if (user_mode(regs) && current->mm->pasid && !current->pasid_activated) { > > Maybe need to add "&& cpu_feature_enabled(X86_FEATURE_ENQCMD)" because > the IA32_PASID MSR is only used when ENQCMD is enabled? > > > + current->pasid_activated = 1; > > + wrmsrl(MSR_IA32_PASID, current->mm->pasid | MSR_IA32_PASID_VALID); > > + return; > > + } > > + > > +endif New version that addresses those issues. Has ugly #ifdef in C code :-( If that's unacceptable, then could create some stub functions, or add a call to __try_fixup_pasid() that's in a file in the iommu code that is only built when CONFIG_IOMMU_SUPPORT is set. But either of those move the details far away from the #GP handler so make extra work for anyone trying to follow along with what is happening here. -Tony --- diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index a58800973aed..5a3c87fd65de 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -528,6 +528,32 @@ static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, #define GPFSTR "general protection fault" +/* + * When a user executes the ENQCMD instruction it will #GP + * fault if the IA32_PASID MSR has not been set up with a + * valid PASID. + * So if the process has been allocated a PASID (mm->pasid) + * AND the IA32_PASID MSR has not been initialized, try to + * fix this #GP by initializing the IA32_PASID MSR. + * If the #GP was for some other reason, it will trigger + * again, but this routine will return false and the #GP + * will be processed. + */ +static void try_fixup_pasid(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) + return false; + +#ifdef CONFIG_IOMMU_SUPPORT + if (current->mm->pasid && !current->pasid_activated) { + current->pasid_activated = 1; + wrmsrl(MSR_IA32_PASID, current->mm->pasid); + return true; + } +#endif + return false; +} + DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) { char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; @@ -536,6 +562,9 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) unsigned long gp_addr; int ret; + if (user_mode(regs) && try_fixup_pasid()) + return; + cond_local_irq_enable(regs); if (static_cpu_has(X86_FEATURE_UMIP)) { From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 721BBC433EF for ; Wed, 29 Sep 2021 18:31:32 +0000 (UTC) Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2FE5361501 for ; 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Wed, 29 Sep 2021 18:31:29 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id CED8060752 for ; Wed, 29 Sep 2021 18:31:29 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9q2RLvzwe9ri for ; Wed, 29 Sep 2021 18:31:29 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.8.0 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by smtp3.osuosl.org (Postfix) with ESMTPS id 227CD60736 for ; Wed, 29 Sep 2021 18:31:28 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10122"; a="223123512" X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="223123512" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 11:31:28 -0700 X-IronPort-AV: E=Sophos;i="5.85,332,1624345200"; d="scan'208";a="563481249" Received: from agluck-desk2.sc.intel.com (HELO agluck-desk2.amr.corp.intel.com) ([10.3.52.146]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Sep 2021 11:31:28 -0700 Date: Wed, 29 Sep 2021 11:31:27 -0700 From: "Luck, Tony" To: Fenghua Yu Subject: Re: [PATCH 5/8] x86/mmu: Add mm-based PASID refcounting Message-ID: References: <87o88jfajo.ffs@tglx> <87k0j6dsdn.ffs@tglx> <87r1d78t2e.ffs@tglx> <75e95acc-6730-ddcf-d722-66e575076256@kernel.org> <877dez8fqu.ffs@tglx> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Cc: "Shankar, Ravi V" , Dave Jiang , Raj Ashok , Peter Zijlstra , the arch/x86 maintainers , Linux Kernel Mailing List , Dave Hansen , iommu@lists.linux-foundation.org, Ingo Molnar , Borislav Petkov , Jacob Jun Pan , Andy Lutomirski , Josh Poimboeuf , Thomas Gleixner X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Wed, Sep 29, 2021 at 06:07:22PM +0000, Fenghua Yu wrote: > Add > +#ifdef CONFIG_IOMMU_SUPPORT > because mm->pasid and current-pasid_activated are defined only if > CONFIG_IOMMU_SUPPORT is defined. > > > + if (user_mode(regs) && current->mm->pasid && !current->pasid_activated) { > > Maybe need to add "&& cpu_feature_enabled(X86_FEATURE_ENQCMD)" because > the IA32_PASID MSR is only used when ENQCMD is enabled? > > > + current->pasid_activated = 1; > > + wrmsrl(MSR_IA32_PASID, current->mm->pasid | MSR_IA32_PASID_VALID); > > + return; > > + } > > + > > +endif New version that addresses those issues. Has ugly #ifdef in C code :-( If that's unacceptable, then could create some stub functions, or add a call to __try_fixup_pasid() that's in a file in the iommu code that is only built when CONFIG_IOMMU_SUPPORT is set. But either of those move the details far away from the #GP handler so make extra work for anyone trying to follow along with what is happening here. -Tony --- diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index a58800973aed..5a3c87fd65de 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -528,6 +528,32 @@ static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, #define GPFSTR "general protection fault" +/* + * When a user executes the ENQCMD instruction it will #GP + * fault if the IA32_PASID MSR has not been set up with a + * valid PASID. + * So if the process has been allocated a PASID (mm->pasid) + * AND the IA32_PASID MSR has not been initialized, try to + * fix this #GP by initializing the IA32_PASID MSR. + * If the #GP was for some other reason, it will trigger + * again, but this routine will return false and the #GP + * will be processed. + */ +static void try_fixup_pasid(void) +{ + if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) + return false; + +#ifdef CONFIG_IOMMU_SUPPORT + if (current->mm->pasid && !current->pasid_activated) { + current->pasid_activated = 1; + wrmsrl(MSR_IA32_PASID, current->mm->pasid); + return true; + } +#endif + return false; +} + DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) { char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; @@ -536,6 +562,9 @@ DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) unsigned long gp_addr; int ret; + if (user_mode(regs) && try_fixup_pasid()) + return; + cond_local_irq_enable(regs); if (static_cpu_has(X86_FEATURE_UMIP)) { _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu