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Tue, 05 Oct 2021 10:00:05 -0700 (PDT) Received: from ripper ([2600:1700:a0:3dc8:205:1bff:fec0:b9b3]) by smtp.gmail.com with ESMTPSA id u2sm3664543otg.51.2021.10.05.10.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 10:00:04 -0700 (PDT) Date: Tue, 5 Oct 2021 10:01:47 -0700 From: Bjorn Andersson To: Srinivasa Rao Mandadapu Cc: agross@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz, tiwai@suse.com, srinivas.kandagatla@linaro.org, rohitkr@codeaurora.org, linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, judyhsiao@chromium.org, Venkata Prasad Potturu Subject: Re: [PATCH] ASoC: qcom: soundwire: Enable soundwire bus clock for version 1.6 Message-ID: References: <1633105471-30928-1-git-send-email-srivasam@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1633105471-30928-1-git-send-email-srivasam@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 01 Oct 09:24 PDT 2021, Srinivasa Rao Mandadapu wrote: > Add support for soundwire 1.6 version to gate RX/TX bus clock. > > Signed-off-by: Venkata Prasad Potturu > Signed-off-by: Srinivasa Rao Mandadapu > --- > drivers/soundwire/qcom.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c > index 0ef79d6..599b3ed 100644 > --- a/drivers/soundwire/qcom.c > +++ b/drivers/soundwire/qcom.c > @@ -127,6 +127,7 @@ struct qcom_swrm_ctrl { > struct device *dev; > struct regmap *regmap; > void __iomem *mmio; > + char __iomem *swrm_hctl_reg; > struct completion broadcast; > struct completion enumeration; > struct work_struct slave_work; > @@ -610,6 +611,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) > val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); > val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); > > + if (ctrl->swrm_hctl_reg) { > + val = ioread32(ctrl->swrm_hctl_reg); > + val &= 0xFFFFFFFD; That's a tricky way of saying: val &= ~BIT(1); That said, naming bit 1 is still a very good thing. > + iowrite32(val, ctrl->swrm_hctl_reg); > + } > + > ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); > > /* Enable Auto enumeration */ > @@ -1200,7 +1207,7 @@ static int qcom_swrm_probe(struct platform_device *pdev) > struct qcom_swrm_ctrl *ctrl; > const struct qcom_swrm_data *data; > int ret; > - u32 val; > + int val, swrm_hctl_reg = 0; > > ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); > if (!ctrl) > @@ -1251,6 +1258,9 @@ static int qcom_swrm_probe(struct platform_device *pdev) > ctrl->bus.port_ops = &qcom_swrm_port_ops; > ctrl->bus.compute_params = &qcom_swrm_compute_params; > > + if (!of_property_read_u32(dev->of_node, "qcom,swrm-hctl-reg", &swrm_hctl_reg)) > + ctrl->swrm_hctl_reg = devm_ioremap(&pdev->dev, swrm_hctl_reg, 0x4); Nack. You may not pull an address to a single register out of an undocumented DT property and blindly ioremap that. And you surely should check for errors here, to avoid magical errors caused by this ioremap failing and your bit not being cleared. Thanks, Bjorn > + > ret = qcom_swrm_get_port_config(ctrl); > if (ret) > goto err_clk; > -- > Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., > is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD7DEC433EF for ; Tue, 5 Oct 2021 17:01:12 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2ABC661163 for ; Tue, 5 Oct 2021 17:01:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 2ABC661163 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; 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Tue, 05 Oct 2021 10:00:04 -0700 (PDT) Date: Tue, 5 Oct 2021 10:01:47 -0700 From: Bjorn Andersson To: Srinivasa Rao Mandadapu Subject: Re: [PATCH] ASoC: qcom: soundwire: Enable soundwire bus clock for version 1.6 Message-ID: References: <1633105471-30928-1-git-send-email-srivasam@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1633105471-30928-1-git-send-email-srivasam@codeaurora.org> Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, bgoswami@codeaurora.org, Venkata Prasad Potturu , linux-arm-msm@vger.kernel.org, plai@codeaurora.org, tiwai@suse.com, agross@kernel.org, robh+dt@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, rohitkr@codeaurora.org, swboyd@chromium.org, judyhsiao@chromium.org, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Fri 01 Oct 09:24 PDT 2021, Srinivasa Rao Mandadapu wrote: > Add support for soundwire 1.6 version to gate RX/TX bus clock. > > Signed-off-by: Venkata Prasad Potturu > Signed-off-by: Srinivasa Rao Mandadapu > --- > drivers/soundwire/qcom.c | 12 +++++++++++- > 1 file changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c > index 0ef79d6..599b3ed 100644 > --- a/drivers/soundwire/qcom.c > +++ b/drivers/soundwire/qcom.c > @@ -127,6 +127,7 @@ struct qcom_swrm_ctrl { > struct device *dev; > struct regmap *regmap; > void __iomem *mmio; > + char __iomem *swrm_hctl_reg; > struct completion broadcast; > struct completion enumeration; > struct work_struct slave_work; > @@ -610,6 +611,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) > val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); > val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); > > + if (ctrl->swrm_hctl_reg) { > + val = ioread32(ctrl->swrm_hctl_reg); > + val &= 0xFFFFFFFD; That's a tricky way of saying: val &= ~BIT(1); That said, naming bit 1 is still a very good thing. > + iowrite32(val, ctrl->swrm_hctl_reg); > + } > + > ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); > > /* Enable Auto enumeration */ > @@ -1200,7 +1207,7 @@ static int qcom_swrm_probe(struct platform_device *pdev) > struct qcom_swrm_ctrl *ctrl; > const struct qcom_swrm_data *data; > int ret; > - u32 val; > + int val, swrm_hctl_reg = 0; > > ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); > if (!ctrl) > @@ -1251,6 +1258,9 @@ static int qcom_swrm_probe(struct platform_device *pdev) > ctrl->bus.port_ops = &qcom_swrm_port_ops; > ctrl->bus.compute_params = &qcom_swrm_compute_params; > > + if (!of_property_read_u32(dev->of_node, "qcom,swrm-hctl-reg", &swrm_hctl_reg)) > + ctrl->swrm_hctl_reg = devm_ioremap(&pdev->dev, swrm_hctl_reg, 0x4); Nack. You may not pull an address to a single register out of an undocumented DT property and blindly ioremap that. And you surely should check for errors here, to avoid magical errors caused by this ioremap failing and your bit not being cleared. Thanks, Bjorn > + > ret = qcom_swrm_get_port_config(ctrl); > if (ret) > goto err_clk; > -- > Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., > is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. >