From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1D85C433EF for ; Fri, 8 Oct 2021 20:39:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DC3DE610E5 for ; Fri, 8 Oct 2021 20:39:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242391AbhJHUlR (ORCPT ); Fri, 8 Oct 2021 16:41:17 -0400 Received: from mail-oi1-f178.google.com ([209.85.167.178]:44004 "EHLO mail-oi1-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231579AbhJHUlO (ORCPT ); Fri, 8 Oct 2021 16:41:14 -0400 Received: by mail-oi1-f178.google.com with SMTP id o4so15232911oia.10; Fri, 08 Oct 2021 13:39:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=YwqJzn+wxrN26HJW0OMW2SzzsY8Wa5uyVVfnaK+wcAo=; b=VHf/bccPmIzCKvyCcXtu40LIrIFB9B7jYpiGEbvDvJ6bFeSSLdNwdj5bdlh9NxzeUl 9kn7z6XhuBXp0hXsv30xXjiPImMe6Pc93GEgsIOz7olv3C2tjRDDSURBjfUtGwtquxd+ IQBgkqjOWLTJf5AVis8Ctp5w7Bg7twp7NA/ai1+aSE1JIKl56NeAuIOpAydRbAnlgxKd WEBBE1K9C9/CRyElzXl1Vr329csqAMjbgmbJc8JpY/9dlW7V1Pr2tOqrPRGO/HHKNV0Q 8qmu7K+GHOFkvPy40gZKtoxHzT3JDKbzkQIWL9NQWbgObv/oH6PAqHHkahjqniJJSWo7 cngg== X-Gm-Message-State: AOAM533Lu0ZgcEFV5BhbhJZEQPiTgkLBNNEdOTtob7CCH+Mw87kzrYo7 y7zqmuKVLm50ixh4m6TCsVAn3tWbGw== X-Google-Smtp-Source: ABdhPJzTsasU3Gsx5AOfjsTwlrtpgS6oDk8MaCZanG1cjAGDO1dahdsN4IfizL5DVpsay8MIuAqzlw== X-Received: by 2002:a05:6808:187:: with SMTP id w7mr9511930oic.140.1633725558240; Fri, 08 Oct 2021 13:39:18 -0700 (PDT) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id v14sm69904ook.2.2021.10.08.13.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Oct 2021 13:39:17 -0700 (PDT) Received: (nullmailer pid 3279811 invoked by uid 1000); Fri, 08 Oct 2021 20:39:16 -0000 Date: Fri, 8 Oct 2021 15:39:16 -0500 From: Rob Herring To: Tony Lindgren Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-omap@vger.kernel.org, Suman Anna , Geert Uytterhoeven , Simon Horman Subject: Re: [PATCH 3/3] dt-bindings: bus: ti-sysc: Update to use yaml binding Message-ID: References: <20211007124858.44011-1-tony@atomide.com> <20211007124858.44011-4-tony@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211007124858.44011-4-tony@atomide.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 07, 2021 at 03:48:58PM +0300, Tony Lindgren wrote: > Update the binding for ti-sysc interconnect target module driver to yaml > format. > > Cc: Rob Herring > Cc: Suman Anna > Signed-off-by: Tony Lindgren > --- > .../devicetree/bindings/bus/ti-sysc.txt | 139 ---------------- > .../devicetree/bindings/bus/ti-sysc.yaml | 150 ++++++++++++++++++ > 2 files changed, 150 insertions(+), 139 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.txt > create mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.yaml > > diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt > deleted file mode 100644 > --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt > +++ /dev/null > @@ -1,139 +0,0 @@ > -Texas Instruments sysc interconnect target module wrapper binding > - > -Texas Instruments SoCs can have a generic interconnect target module > -hardware for devices connected to various interconnects such as L3 > -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc > -is mostly used for interaction between module and PRCM. It participates > -in the OCP Disconnect Protocol but other than that is mostly independent > -of the interconnect. > - > -Each interconnect target module can have one or more devices connected to > -it. There is a set of control registers for managing interconnect target > -module clocks, idle modes and interconnect level resets for the module. > - > -These control registers are sprinkled into the unused register address > -space of the first child device IP block managed by the interconnect > -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. > - > -Required standard properties: > - > -- compatible shall be one of the following generic types: > - > - "ti,sysc" > - "ti,sysc-omap2" > - "ti,sysc-omap4" > - "ti,sysc-omap4-simple" > - > - or one of the following derivative types for hardware > - needing special workarounds: > - > - "ti,sysc-omap2-timer" > - "ti,sysc-omap4-timer" > - "ti,sysc-omap3430-sr" > - "ti,sysc-omap3630-sr" > - "ti,sysc-omap4-sr" > - "ti,sysc-omap3-sham" > - "ti,sysc-omap-aes" > - "ti,sysc-mcasp" > - "ti,sysc-dra7-mcasp" > - "ti,sysc-usb-host-fs" > - "ti,sysc-dra7-mcan" > - "ti,sysc-pruss" > - > -- reg shall have register areas implemented for the interconnect > - target module in question such as revision, sysc and syss > - > -- reg-names shall contain the register names implemented for the > - interconnect target module in question such as > - "rev, "sysc", and "syss" > - > -- ranges shall contain the interconnect target module IO range > - available for one or more child device IP blocks managed > - by the interconnect target module, the ranges may include > - multiple ranges such as device L4 range for control and > - parent L3 range for DMA access > - > -Optional properties: > - > -- ti,sysc-mask shall contain mask of supported register bits for the > - SYSCONFIG register as documented in the Technical Reference > - Manual (TRM) for the interconnect target module > - > -- ti,sysc-midle list of master idle modes supported by the interconnect > - target module as documented in the TRM for SYSCONFIG > - register MIDLEMODE bits > - > -- ti,sysc-sidle list of slave idle modes supported by the interconnect > - target module as documented in the TRM for SYSCONFIG > - register SIDLEMODE bits > - > -- ti,sysc-delay-us delay needed after OCP softreset before accssing > - SYSCONFIG register again > - > -- ti,syss-mask optional mask of reset done status bits as described in the > - TRM for SYSSTATUS registers, typically 1 with some devices > - having separate reset done bits for children like OHCI and > - EHCI > - > -- clocks clock specifier for each name in the clock-names as > - specified in the binding documentation for ti-clkctrl, > - typically available for all interconnect targets on TI SoCs > - based on omap4 except if it's read-only register in hwauto > - mode as for example omap4 L4_CFG_CLKCTRL > - > -- clock-names should contain at least "fck", and optionally also "ick" > - depending on the SoC and the interconnect target module, > - some interconnect target modules also need additional > - optional clocks that can be specified as listed in TRM > - for the related CLKCTRL register bits 8 to 15 such as > - "dbclk" or "clk32k" depending on their role > - > -- ti,hwmods optional TI interconnect module name to use legacy > - hwmod platform data > - > -- ti,no-reset-on-init interconnect target module should not be reset at init > - > -- ti,no-idle-on-init interconnect target module should not be idled at init > - > -- ti,no-idle interconnect target module should not be idled > - > -Example: Single instance of MUSB controller on omap4 using interconnect ranges > -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): > - > - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ > - compatible = "ti,sysc-omap2"; > - ti,hwmods = "usb_otg_hs"; > - reg = <0x2b400 0x4>, > - <0x2b404 0x4>, > - <0x2b408 0x4>; > - reg-names = "rev", "sysc", "syss"; > - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; > - clock-names = "fck"; > - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > - SYSC_OMAP2_SOFTRESET | > - SYSC_OMAP2_AUTOIDLE)>; > - ti,sysc-midle = , > - , > - ; > - ti,sysc-sidle = , > - , > - , > - ; > - ti,syss-mask = <1>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x2b000 0x1000>; > - > - usb_otg_hs: otg@0 { > - compatible = "ti,omap4-musb"; > - reg = <0x0 0x7ff>; > - interrupts = , > - ; > - usb-phy = <&usb2_phy>; > - ... > - }; > - }; > - > -Note that other SoCs, such as am335x can have multiple child devices. On am335x > -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA > -instance as children of a single interconnect target module. > diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.yaml b/Documentation/devicetree/bindings/bus/ti-sysc.yaml > new file mode 100644 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/ti-sysc.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Texas Instruments interconnect target module binding > + > +maintainers: > + - Tony Lindgren > + > +description: | > + Texas Instruments SoCs can have a generic interconnect target module > + for devices connected to various interconnects such as L3 interconnect > + using Arteris NoC, and L4 interconnect using Sonics s3220. This module > + is mostly used for interaction between module and Power, Reset and Clock > + Manager PRCM. It participates in the OCP Disconnect Protocol, but other > + than that it is mostly independent of the interconnect. > + > + Each interconnect target module can have one or more devices connected to > + it. There is a set of control registers for managing the interconnect target > + module clocks, idle modes and interconnect level resets. > + > + The interconnect target module control registers are sprinkled into the > + unused register address space of the first child device IP block managed by > + the interconnect target module. Typically the register names are REVISION, > + SYSCONFIG and SYSSTATUS. > + > +properties: > + $nodename: > + pattern: "^target-module(@[0-9a-f]+)?$" > + > + compatible: > + oneOf: > + - items: > + - enum: > + - ti,sysc-omap2 > + - ti,sysc-omap2 > + - ti,sysc-omap4 > + - ti,sysc-omap4-simple > + - ti,sysc-omap2-timer > + - ti,sysc-omap4-timer > + - ti,sysc-omap3430-sr > + - ti,sysc-omap3630-sr > + - ti,sysc-omap4-sr > + - ti,sysc-omap3-sham > + - ti,sysc-omap-aes > + - ti,sysc-mcasp > + - ti,sysc-dra7-mcasp > + - ti,sysc-usb-host-fs > + - ti,sysc-dra7-mcan > + - ti,sysc-pruss > + - const: ti,sysc > + - items: > + - const: ti,sysc This doesn't really match what the old doc said nor the old example. Fine to fix in the conversion if wrong, but just highlight that in the commit msg. > + > + reg: true Any number of register areas is valid? > + > + reg-names: true You've thrown out the names defined before. > + > + clocks: true Any number of clocks is valid? > + > + clock-names: true You've thrown out the names defined before. > + > + power-domains: true How many? > + > + '#address-cells': > + enum: [ 1, 2 ] > + > + '#size-cells': > + enum: [ 1, 2 ] > + > + ranges: true > + > + ti,sysc-mask: > + description: Mask of supported register bits for the SYSCONFIG register > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + ti,sysc-midle: > + description: List of hardware supported idle modes > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + ti,sysc-sidle: > + description: List of hardware supported idle modes > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + ti,syss-mask: > + description: Mask of supported register bits for the SYSSTATUS register > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + ti,sysc-delay-us: > + description: Delay needed after OCP softreset before accessing SYCONFIG > + default: 0 > + minimum: 0 > + maximum: 2 > + > + ti,no-reset-on-init: > + description: Interconnect target module shall not be reset at init > + type: boolean > + > + ti,no-idle-on-init: > + description: Interconnect target module shall not be idled at init > + type: boolean > + > + ti,no-idle: > + description: Interconnect target module shall not be idled > + type: boolean > + > + ti,hwmods: > + description: Interconnect module name to use with legacy hwmod data > + $ref: /schemas/types.yaml#/definitions/string > + deprecated: true > + > +required: > + - compatible > + - '#address-cells' > + - '#size-cells' > + - ranges > + > +additionalProperties: true This can be restricted to child nodes only? If so: additionalProperties: type: object > + > +examples: > + - | > + #include > + #include > + > + target-module@2b000 { > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "usb_otg_hs"; > + reg = <0x2b400 0x4>, > + <0x2b404 0x4>, > + <0x2b408 0x4>; > + reg-names = "rev", "sysc", "syss"; > + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; > + clock-names = "fck"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-midle = , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x2b000 0x1000>; > + }; > -- > 2.33.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4638BC433EF for ; Fri, 8 Oct 2021 20:41:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FBD161152 for ; Fri, 8 Oct 2021 20:41:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0FBD161152 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gg6fBPWzTNU98ceFSN2GkaDUn/YmG5MSmOPhrmmHFlk=; b=f9DxnreGnXD/A1 1X9msjkvq810UQWJuBj7Va0oGNgI+PP2qy+X8qiMsQVnF2mfaLiYmRw6tw7XDbotS8VtyIOfwHMdi A+l7xCy/qxkM0BYYzkKPuQeYGvTHs4RR+16umhYr80wdqsbiVNusI4c4DWgBFfvG5rjdQJHaNSe7R zxx/8C4eKtC760xbWck7mEQ9fgKarn+9bNZ74iK5uomWkECmTWeHk8RefscLQ1lAs3OdyUuNYVOgI OKKhHq7ZvHffgtmkcy18dZs3rCPLlwwWsh3AcRAOvC83GnFP6sXQDvU/kNTP5fiukdhbwWuHK3TCK RkDBmBq4kJkr3uWRUMNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYweK-0047Me-VD; Fri, 08 Oct 2021 20:39:25 +0000 Received: from mail-oi1-f171.google.com ([209.85.167.171]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mYweF-0047Le-Nv for linux-arm-kernel@lists.infradead.org; Fri, 08 Oct 2021 20:39:22 +0000 Received: by mail-oi1-f171.google.com with SMTP id o4so15232914oia.10 for ; Fri, 08 Oct 2021 13:39:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=YwqJzn+wxrN26HJW0OMW2SzzsY8Wa5uyVVfnaK+wcAo=; b=P/IbJMBBYj4yLaUaGIxRDvcP64zISSN36P0TixHpr0BlEYbhiDrx+1+HhCGHHpftYQ DPfJBsSqdqfd2WQW6G4l1oVF7zlN7UYlL5VPbMdlaYkD1BMjLVaZheMZqpCvNdvWmrYp UG3VVqEWQo0P562Vq/06tCR7xD/Xt586qqIn4ruxjcUibF8sbjrzu24aCjp+lj40Ui1x PKahsGBCx8iVxWbHFiQGf3kTG0J5VXUqYJs9oKmISLYYsXEafGjCaOQHPWhEY5ab5YdT NVIcNfmVaZdDTZgA6k4yOt1kKdYLrRcTTLUZIynp5sfdBm7NxHqSC5Vv8RLFS6VNGDNE 80KQ== X-Gm-Message-State: AOAM5309OIVzPgOgwBpSp7wRzelseFSaFM1lrsDqFerWy2IfiC6BG7BZ tMBPuToSQB12fUXZpp+1lQ== X-Google-Smtp-Source: ABdhPJzTsasU3Gsx5AOfjsTwlrtpgS6oDk8MaCZanG1cjAGDO1dahdsN4IfizL5DVpsay8MIuAqzlw== X-Received: by 2002:a05:6808:187:: with SMTP id w7mr9511930oic.140.1633725558240; Fri, 08 Oct 2021 13:39:18 -0700 (PDT) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id v14sm69904ook.2.2021.10.08.13.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Oct 2021 13:39:17 -0700 (PDT) Received: (nullmailer pid 3279811 invoked by uid 1000); Fri, 08 Oct 2021 20:39:16 -0000 Date: Fri, 8 Oct 2021 15:39:16 -0500 From: Rob Herring To: Tony Lindgren Subject: Re: [PATCH 3/3] dt-bindings: bus: ti-sysc: Update to use yaml binding Message-ID: References: <20211007124858.44011-1-tony@atomide.com> <20211007124858.44011-4-tony@atomide.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211007124858.44011-4-tony@atomide.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211008_133919_845483_07B8B012 X-CRM114-Status: GOOD ( 41.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org, Geert Uytterhoeven , linux-kernel@vger.kernel.org, Simon Horman , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 07, 2021 at 03:48:58PM +0300, Tony Lindgren wrote: > Update the binding for ti-sysc interconnect target module driver to yaml > format. > > Cc: Rob Herring > Cc: Suman Anna > Signed-off-by: Tony Lindgren > --- > .../devicetree/bindings/bus/ti-sysc.txt | 139 ---------------- > .../devicetree/bindings/bus/ti-sysc.yaml | 150 ++++++++++++++++++ > 2 files changed, 150 insertions(+), 139 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.txt > create mode 100644 Documentation/devicetree/bindings/bus/ti-sysc.yaml > > diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt > deleted file mode 100644 > --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt > +++ /dev/null > @@ -1,139 +0,0 @@ > -Texas Instruments sysc interconnect target module wrapper binding > - > -Texas Instruments SoCs can have a generic interconnect target module > -hardware for devices connected to various interconnects such as L3 > -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc > -is mostly used for interaction between module and PRCM. It participates > -in the OCP Disconnect Protocol but other than that is mostly independent > -of the interconnect. > - > -Each interconnect target module can have one or more devices connected to > -it. There is a set of control registers for managing interconnect target > -module clocks, idle modes and interconnect level resets for the module. > - > -These control registers are sprinkled into the unused register address > -space of the first child device IP block managed by the interconnect > -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. > - > -Required standard properties: > - > -- compatible shall be one of the following generic types: > - > - "ti,sysc" > - "ti,sysc-omap2" > - "ti,sysc-omap4" > - "ti,sysc-omap4-simple" > - > - or one of the following derivative types for hardware > - needing special workarounds: > - > - "ti,sysc-omap2-timer" > - "ti,sysc-omap4-timer" > - "ti,sysc-omap3430-sr" > - "ti,sysc-omap3630-sr" > - "ti,sysc-omap4-sr" > - "ti,sysc-omap3-sham" > - "ti,sysc-omap-aes" > - "ti,sysc-mcasp" > - "ti,sysc-dra7-mcasp" > - "ti,sysc-usb-host-fs" > - "ti,sysc-dra7-mcan" > - "ti,sysc-pruss" > - > -- reg shall have register areas implemented for the interconnect > - target module in question such as revision, sysc and syss > - > -- reg-names shall contain the register names implemented for the > - interconnect target module in question such as > - "rev, "sysc", and "syss" > - > -- ranges shall contain the interconnect target module IO range > - available for one or more child device IP blocks managed > - by the interconnect target module, the ranges may include > - multiple ranges such as device L4 range for control and > - parent L3 range for DMA access > - > -Optional properties: > - > -- ti,sysc-mask shall contain mask of supported register bits for the > - SYSCONFIG register as documented in the Technical Reference > - Manual (TRM) for the interconnect target module > - > -- ti,sysc-midle list of master idle modes supported by the interconnect > - target module as documented in the TRM for SYSCONFIG > - register MIDLEMODE bits > - > -- ti,sysc-sidle list of slave idle modes supported by the interconnect > - target module as documented in the TRM for SYSCONFIG > - register SIDLEMODE bits > - > -- ti,sysc-delay-us delay needed after OCP softreset before accssing > - SYSCONFIG register again > - > -- ti,syss-mask optional mask of reset done status bits as described in the > - TRM for SYSSTATUS registers, typically 1 with some devices > - having separate reset done bits for children like OHCI and > - EHCI > - > -- clocks clock specifier for each name in the clock-names as > - specified in the binding documentation for ti-clkctrl, > - typically available for all interconnect targets on TI SoCs > - based on omap4 except if it's read-only register in hwauto > - mode as for example omap4 L4_CFG_CLKCTRL > - > -- clock-names should contain at least "fck", and optionally also "ick" > - depending on the SoC and the interconnect target module, > - some interconnect target modules also need additional > - optional clocks that can be specified as listed in TRM > - for the related CLKCTRL register bits 8 to 15 such as > - "dbclk" or "clk32k" depending on their role > - > -- ti,hwmods optional TI interconnect module name to use legacy > - hwmod platform data > - > -- ti,no-reset-on-init interconnect target module should not be reset at init > - > -- ti,no-idle-on-init interconnect target module should not be idled at init > - > -- ti,no-idle interconnect target module should not be idled > - > -Example: Single instance of MUSB controller on omap4 using interconnect ranges > -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): > - > - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ > - compatible = "ti,sysc-omap2"; > - ti,hwmods = "usb_otg_hs"; > - reg = <0x2b400 0x4>, > - <0x2b404 0x4>, > - <0x2b408 0x4>; > - reg-names = "rev", "sysc", "syss"; > - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; > - clock-names = "fck"; > - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > - SYSC_OMAP2_SOFTRESET | > - SYSC_OMAP2_AUTOIDLE)>; > - ti,sysc-midle = , > - , > - ; > - ti,sysc-sidle = , > - , > - , > - ; > - ti,syss-mask = <1>; > - #address-cells = <1>; > - #size-cells = <1>; > - ranges = <0 0x2b000 0x1000>; > - > - usb_otg_hs: otg@0 { > - compatible = "ti,omap4-musb"; > - reg = <0x0 0x7ff>; > - interrupts = , > - ; > - usb-phy = <&usb2_phy>; > - ... > - }; > - }; > - > -Note that other SoCs, such as am335x can have multiple child devices. On am335x > -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA > -instance as children of a single interconnect target module. > diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.yaml b/Documentation/devicetree/bindings/bus/ti-sysc.yaml > new file mode 100644 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/ti-sysc.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Texas Instruments interconnect target module binding > + > +maintainers: > + - Tony Lindgren > + > +description: | > + Texas Instruments SoCs can have a generic interconnect target module > + for devices connected to various interconnects such as L3 interconnect > + using Arteris NoC, and L4 interconnect using Sonics s3220. This module > + is mostly used for interaction between module and Power, Reset and Clock > + Manager PRCM. It participates in the OCP Disconnect Protocol, but other > + than that it is mostly independent of the interconnect. > + > + Each interconnect target module can have one or more devices connected to > + it. There is a set of control registers for managing the interconnect target > + module clocks, idle modes and interconnect level resets. > + > + The interconnect target module control registers are sprinkled into the > + unused register address space of the first child device IP block managed by > + the interconnect target module. Typically the register names are REVISION, > + SYSCONFIG and SYSSTATUS. > + > +properties: > + $nodename: > + pattern: "^target-module(@[0-9a-f]+)?$" > + > + compatible: > + oneOf: > + - items: > + - enum: > + - ti,sysc-omap2 > + - ti,sysc-omap2 > + - ti,sysc-omap4 > + - ti,sysc-omap4-simple > + - ti,sysc-omap2-timer > + - ti,sysc-omap4-timer > + - ti,sysc-omap3430-sr > + - ti,sysc-omap3630-sr > + - ti,sysc-omap4-sr > + - ti,sysc-omap3-sham > + - ti,sysc-omap-aes > + - ti,sysc-mcasp > + - ti,sysc-dra7-mcasp > + - ti,sysc-usb-host-fs > + - ti,sysc-dra7-mcan > + - ti,sysc-pruss > + - const: ti,sysc > + - items: > + - const: ti,sysc This doesn't really match what the old doc said nor the old example. Fine to fix in the conversion if wrong, but just highlight that in the commit msg. > + > + reg: true Any number of register areas is valid? > + > + reg-names: true You've thrown out the names defined before. > + > + clocks: true Any number of clocks is valid? > + > + clock-names: true You've thrown out the names defined before. > + > + power-domains: true How many? > + > + '#address-cells': > + enum: [ 1, 2 ] > + > + '#size-cells': > + enum: [ 1, 2 ] > + > + ranges: true > + > + ti,sysc-mask: > + description: Mask of supported register bits for the SYSCONFIG register > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + ti,sysc-midle: > + description: List of hardware supported idle modes > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + ti,sysc-sidle: > + description: List of hardware supported idle modes > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + ti,syss-mask: > + description: Mask of supported register bits for the SYSSTATUS register > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + ti,sysc-delay-us: > + description: Delay needed after OCP softreset before accessing SYCONFIG > + default: 0 > + minimum: 0 > + maximum: 2 > + > + ti,no-reset-on-init: > + description: Interconnect target module shall not be reset at init > + type: boolean > + > + ti,no-idle-on-init: > + description: Interconnect target module shall not be idled at init > + type: boolean > + > + ti,no-idle: > + description: Interconnect target module shall not be idled > + type: boolean > + > + ti,hwmods: > + description: Interconnect module name to use with legacy hwmod data > + $ref: /schemas/types.yaml#/definitions/string > + deprecated: true > + > +required: > + - compatible > + - '#address-cells' > + - '#size-cells' > + - ranges > + > +additionalProperties: true This can be restricted to child nodes only? If so: additionalProperties: type: object > + > +examples: > + - | > + #include > + #include > + > + target-module@2b000 { > + compatible = "ti,sysc-omap2", "ti,sysc"; > + ti,hwmods = "usb_otg_hs"; > + reg = <0x2b400 0x4>, > + <0x2b404 0x4>, > + <0x2b408 0x4>; > + reg-names = "rev", "sysc", "syss"; > + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; > + clock-names = "fck"; > + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | > + SYSC_OMAP2_SOFTRESET | > + SYSC_OMAP2_AUTOIDLE)>; > + ti,sysc-midle = , > + , > + ; > + ti,sysc-sidle = , > + , > + , > + ; > + ti,syss-mask = <1>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x2b000 0x1000>; > + }; > -- > 2.33.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel