From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38185C433F5 for ; Tue, 12 Oct 2021 16:46:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 21A3B601FA for ; Tue, 12 Oct 2021 16:46:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231922AbhJLQsP (ORCPT ); Tue, 12 Oct 2021 12:48:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231905AbhJLQsM (ORCPT ); Tue, 12 Oct 2021 12:48:12 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A29FC061570 for ; Tue, 12 Oct 2021 09:46:10 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id e7so14412261pgk.2 for ; Tue, 12 Oct 2021 09:46:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to; bh=WxtJ6kTMjB335FQT7eQ0eT+70TQDiMjlEAzZlxMqe30=; b=bKOflXsLFzC3VU2LBpYLCOQSqWZeASP6ZYpwtMXyXCQ24DvBTaHGYfF64wgjZDKsla LpPBv3FFCMFYsmS+evB4X2EmqUiQKWI7oaGecXjhcm4t10DJpJr2vmOVqhi9jQY9eJXi 9a6BmBu4332+d7Ju7hIbBp1ZnLa2LGcKGoTyDvfvwICGsr9y4cx2bX3A4DiwdeDSleK6 ADuM4LSQ5VFYhTx9WO6iia8tKPWVl1qqkwJiMW8Bt/75nqycZwR4exTh/O2RXjV8cMPx kBII7YI8Dhm4R3Hr2cD4FnOV4Ddw1flpexyUS8KyOwUiN8m8eaoqUtQ2eqAhi9HeeGkk 8HoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=WxtJ6kTMjB335FQT7eQ0eT+70TQDiMjlEAzZlxMqe30=; b=yfUOYtbnZTWdhbJj9b6Z+tOcuyBuu7Er5f3UJrbGlYUGrverTzqMriecQXg72tCeUf zHGxOQJvDXem6uqTob+AN9eyCx0SrqSbeJ9MtelaWGhn1RjsPWz3ZWOMNCtPnozy97s7 8inFHDDxdlNm+BI/k5mv4yKgjoPMMBsmKMvQh0RfeQvCU+db3oNdFzJtBB2f1WoxIKwT OrTsQrUTHYzDYBCwu5cuzccYZJHKr5KXGi3X5HYHV1qwBFtqjJgA2CduTC8zSGaJGCpC 73Uqz7LVfgymUHz9XYSnl7pwkoNFL9JULOIMLnhJHULLSuF7P8F8fZ+b4/HHbqtqiYpx tDQQ== X-Gm-Message-State: AOAM531213evwpUUJkSXF823nLWguvG1ockWYNOzPKtlAiD+L1qIYrFf N12w3334YToUXqqV36SpV3H9PQ== X-Google-Smtp-Source: ABdhPJwqjQYiIu9GVaeWoRMdEp/IOLk9KZQUl3zIehqyu0N4NWB1pHgyw7wIiEOvLESAmyrDCLnUww== X-Received: by 2002:a63:564a:: with SMTP id g10mr23601412pgm.199.1634057168886; Tue, 12 Oct 2021 09:46:08 -0700 (PDT) Received: from google.com (157.214.185.35.bc.googleusercontent.com. [35.185.214.157]) by smtp.gmail.com with ESMTPSA id z19sm11467471pfj.156.2021.10.12.09.46.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 09:46:08 -0700 (PDT) Date: Tue, 12 Oct 2021 16:46:04 +0000 From: Sean Christopherson To: Atish Patra Cc: "kvm-riscv@lists.infradead.org" , "linux-riscv@lists.infradead.org" , "vincent.chen@sifive.com" , Anup Patel , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "wangkefeng.wang@huawei.com" , "kvm@vger.kernel.org" , "pbonzini@redhat.com" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v3 5/5] RISC-V: Add SBI HSM extension in KVM Message-ID: References: <20211008032036.2201971-1-atish.patra@wdc.com> <20211008032036.2201971-6-atish.patra@wdc.com> <0383b5cacb25e9dc293d891284df9f4cbc06ee3a.camel@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 11, 2021, Atish Patra wrote: > On Mon, 2021-10-11 at 14:32 +0000, Sean Christopherson wrote: > > On Mon, Oct 11, 2021, Atish Patra wrote: > > > On Fri, 2021-10-08 at 15:02 +0000, Sean Christopherson wrote: > > > > On Thu, Oct 07, 2021, Atish Patra wrote: > > > > > +       preempt_disable(); > > > > > +       loaded = (vcpu->cpu != -1); > > > > > +       if (loaded) > > > > > +               kvm_arch_vcpu_put(vcpu); > > > > > > > > Oof.  Looks like this pattern was taken from arm64.  > > > > > > Yes. This part is similar to arm64 because the same race condition > > > can > > > happen in riscv due to save/restore of CSRs during reset. > > > > > > > > > > Is there really no better approach to handling this?  I don't see > > > > anything  in kvm_riscv_reset_vcpu() that will obviously break if the > > > > vCPU is  loaded.  If the goal is purely to effect a CSR reset via > > > > kvm_arch_vcpu_load(), then why not just factor out a helper to do > > > > exactly that? > > > > What about the question here? > > Are you suggesting to factor the csr reset part to a different function? More or less. I'm mostly asking why putting the vCPU is necessary. > > > > >  void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) > > > > >  { > > > > > +       /** > > > > > +        * vcpu with id 0 is the designated boot cpu. > > > > > +        * Keep all vcpus with non-zero cpu id in power-off > > > > > state > > > > > so that they > > > > > +        * can brought to online using SBI HSM extension. > > > > > +        */ > > > > > +       if (vcpu->vcpu_idx != 0) > > > > > +               kvm_riscv_vcpu_power_off(vcpu); > > > > > > > > Why do this in postcreate? > > > > > > > > > > Because we need to absolutely sure that the vcpu is created. It is > > > cleaner in this way rather than doing this here at the end of > > > kvm_arch_vcpu_create. create_vcpu can also fail after > > > kvm_arch_vcpu_create returns. > > > > But kvm_riscv_vcpu_power_off() doesn't doesn't anything outside of the > > vCPU.  It clears vcpu->arch.power_off, makes a request, and kicks the > > vCPU.  None of that has side effects to anything else in KVM.  If the vCPU > > isn't created successfully, it gets deleted and nothing ever sees that > > state change. > > I am assuming that you are suggesting to add this logic at the end of > the kvm_arch_vcpu_create() instead of kvm_arch_vcpu_postcreate(). > > vcpu_idx is assigned after kvm_arch_vcpu_create() returns in the > kvm_vm_ioctl_create_vcpu. kvm_arch_vcpu_postcreate() is the arch hookup > after vcpu_idx is assigned. Ah, it's the consumption of vcpu->vcpu_idx that's problematic. Thanks! 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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id z19sm11467471pfj.156.2021.10.12.09.46.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Oct 2021 09:46:08 -0700 (PDT) Date: Tue, 12 Oct 2021 16:46:04 +0000 From: Sean Christopherson To: Atish Patra Cc: "kvm-riscv@lists.infradead.org" , "linux-riscv@lists.infradead.org" , "vincent.chen@sifive.com" , Anup Patel , "paul.walmsley@sifive.com" , "palmer@dabbelt.com" , "wangkefeng.wang@huawei.com" , "kvm@vger.kernel.org" , "pbonzini@redhat.com" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v3 5/5] RISC-V: Add SBI HSM extension in KVM Message-ID: References: <20211008032036.2201971-1-atish.patra@wdc.com> <20211008032036.2201971-6-atish.patra@wdc.com> <0383b5cacb25e9dc293d891284df9f4cbc06ee3a.camel@wdc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211012_094612_258890_497AE58D X-CRM114-Status: GOOD ( 29.93 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Oct 11, 2021, Atish Patra wrote: > On Mon, 2021-10-11 at 14:32 +0000, Sean Christopherson wrote: > > On Mon, Oct 11, 2021, Atish Patra wrote: > > > On Fri, 2021-10-08 at 15:02 +0000, Sean Christopherson wrote: > > > > On Thu, Oct 07, 2021, Atish Patra wrote: > > > > > +=A0=A0=A0=A0=A0=A0=A0preempt_disable(); > > > > > +=A0=A0=A0=A0=A0=A0=A0loaded =3D (vcpu->cpu !=3D -1); > > > > > +=A0=A0=A0=A0=A0=A0=A0if (loaded) > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0kvm_arch_vcpu_put(v= cpu); > > > > = > > > > Oof.=A0 Looks like this pattern was taken from arm64.=A0 > > > = > > > Yes. This part is similar to arm64 because the same race condition > > > can > > > happen in riscv due to save/restore of CSRs during reset. > > > = > > > = > > > > Is there really no better approach to handling this?=A0 I don't see > > > > anything =A0in kvm_riscv_reset_vcpu() that will obviously break if = the > > > > vCPU is =A0loaded.=A0 If the goal is purely to effect a CSR reset v= ia > > > > kvm_arch_vcpu_load(), then why not just factor out a helper to do > > > > exactly that? > > = > > What about the question here? > = > Are you suggesting to factor the csr reset part to a different function? More or less. I'm mostly asking why putting the vCPU is necessary. > > > > > =A0void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) > > > > > =A0{ > > > > > +=A0=A0=A0=A0=A0=A0=A0/** > > > > > +=A0=A0=A0=A0=A0=A0=A0 * vcpu with id 0 is the designated boot cp= u. > > > > > +=A0=A0=A0=A0=A0=A0=A0 * Keep all vcpus with non-zero cpu id in p= ower-off > > > > > state > > > > > so that they > > > > > +=A0=A0=A0=A0=A0=A0=A0 * can brought to online using SBI HSM exte= nsion. > > > > > +=A0=A0=A0=A0=A0=A0=A0 */ > > > > > +=A0=A0=A0=A0=A0=A0=A0if (vcpu->vcpu_idx !=3D 0) > > > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0kvm_riscv_vcpu_powe= r_off(vcpu); > > > > = > > > > Why do this in postcreate? > > > > = > > > = > > > Because we need to absolutely sure that the vcpu is created. It is > > > cleaner in this way rather than doing this here at the end of > > > kvm_arch_vcpu_create. create_vcpu can also fail after > > > kvm_arch_vcpu_create returns. > > = > > But kvm_riscv_vcpu_power_off() doesn't doesn't anything outside of the > > vCPU.=A0 It clears vcpu->arch.power_off, makes a request, and kicks the > > vCPU.=A0 None of that has side effects to anything else in KVM.=A0 If t= he vCPU > > isn't created successfully, it gets deleted and nothing ever sees that > > state change. > = > I am assuming that you are suggesting to add this logic at the end of > the kvm_arch_vcpu_create() instead of kvm_arch_vcpu_postcreate(). > = > vcpu_idx is assigned after kvm_arch_vcpu_create() returns in the > kvm_vm_ioctl_create_vcpu. kvm_arch_vcpu_postcreate() is the arch hookup > after vcpu_idx is assigned. Ah, it's the consumption of vcpu->vcpu_idx that's problematic. Thanks! _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv