From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C8D7C433F5 for ; Tue, 12 Oct 2021 23:49:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1334160E94 for ; Tue, 12 Oct 2021 23:49:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1334160E94 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=etezian.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 351D06E042; Tue, 12 Oct 2021 23:49:14 +0000 (UTC) X-Greylist: delayed 1799 seconds by postgrey-1.36 at gabe; Tue, 12 Oct 2021 23:49:12 UTC Received: from 6.mo560.mail-out.ovh.net (6.mo560.mail-out.ovh.net [87.98.165.38]) by gabe.freedesktop.org (Postfix) with ESMTPS id C7DE06E042 for ; Tue, 12 Oct 2021 23:49:12 +0000 (UTC) Received: from player762.ha.ovh.net (unknown [10.110.115.164]) by mo560.mail-out.ovh.net (Postfix) with ESMTP id 68C5A224FE for ; Tue, 12 Oct 2021 23:11:16 +0000 (UTC) Received: from etezian.org (unknown [31.22.55.47]) (Authenticated sender: andi@etezian.org) by player762.ha.ovh.net (Postfix) with ESMTPSA id 72816231C9D79; Tue, 12 Oct 2021 23:11:05 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-97G0022a29f053-239c-4698-bc61-1bf3f12af407, C786CB9E79FC7D8AF81679FEBE5E79C8CF9BC842) smtp.auth=andi@etezian.org X-OVh-ClientIp: 31.22.55.47 Date: Wed, 13 Oct 2021 01:11:04 +0200 From: Andi Shyti To: Matt Roper Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Tvrtko Ursulin , Matthew Auld , Daniele Ceraolo Spurio , Joonas Lahtinen , Paulo Zanoni , Andi Shyti , Michal Wajdeczko Subject: Re: [Intel-gfx] [PATCH v2 11/11] drm/i915/xehpsdv: Initialize multi-tiles Message-ID: References: <20211008215635.2026385-12-matthew.d.roper@intel.com> <20211008233310.2034639-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211008233310.2034639-1-matthew.d.roper@intel.com> X-Ovh-Tracer-Id: 1590896571445742288 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddrvddtledgudejucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepfffhvffukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeetnhguihcuufhhhihtihcuoegrnhguihesvghtvgiiihgrnhdrohhrgheqnecuggftrfgrthhtvghrnheptdfgudduhfefueeujeefieehtdeftefggeevhefgueellefhudetgeeikeduieefnecukfhppedtrddtrddtrddtpdefuddrvddvrdehhedrgeejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepphhlrgihvghrjeeivddrhhgrrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegrnhguihesvghtvgiiihgrnhdrohhrghdprhgtphhtthhopegurhhiqdguvghvvghlsehlihhsthhsrdhfrhgvvgguvghskhhtohhprdhorhhg X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Tvrtko and Matt, [...] > -#define I915_MAX_TILES 4 > - struct intel_gt *gts[I915_MAX_TILES]; > +#define I915_MAX_GTS 4 > + struct intel_gt *gts[I915_MAX_GTS]; let's call it MAX_GTS already in patch 5 so that we can avoid a rename. BTW, out of the scope of this patch but if we can read the number of tiles, why don't we make this dynamic? We already have a "dynamic" version for_each_gt() in probe_gts(). [...] > > struct { > struct i915_gem_contexts { > @@ -1724,6 +1726,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > > #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) > #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) > +#define HAS_REMOTE_TILES(dev_priv) (INTEL_INFO(dev_priv)->has_remote_tiles) s/dev_priv/i915 [...] > +static const struct intel_gt_definition xehp_sdv_gts[] = { > + { > + .type = GT_TILE, > + .name = "Remote Tile GT", > + .mapping_base = SZ_16M, > + .engine_mask = XE_HP_SDV_ENGINES, > + > + }, > + { > + .type = GT_TILE, > + .name = "Remote Tile GT", > + .mapping_base = SZ_16M * 2, > + .engine_mask = XE_HP_SDV_ENGINES, > + > + }, > + { > + .type = GT_TILE, > + .name = "Remote Tile GT", why don't we call it "Remote Tile GT " or similar? [...] Andi