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Date: Thu, 21 Oct 2021 23:55:34 +0200
From: =?iso-8859-2?Q?Micha=B3_Miros=B3aw?= <mirq-linux@rere.qmqm.pl>
To: Nathan Chancellor <nathan@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Nick Desaulniers <ndesaulniers@google.com>,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	llvm@lists.linux.dev
Subject: Re: [PATCH] soc/tegra: fuse: Fix bitwise vs. logical OR warning
Message-ID: <YXHh1lVCzVnyTiZv@qmqm.qmqm.pl>
References: <20211021214500.2388146-1-nathan@kernel.org>
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In-Reply-To: <20211021214500.2388146-1-nathan@kernel.org>

On Thu, Oct 21, 2021 at 02:45:00PM -0700, Nathan Chancellor wrote:
[...]
> --- a/drivers/soc/tegra/fuse/speedo-tegra20.c
> +++ b/drivers/soc/tegra/fuse/speedo-tegra20.c
> @@ -69,7 +69,7 @@ void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
>  
>  	val = 0;
>  	for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
> -		reg = tegra_fuse_read_spare(i) |
> +		reg = tegra_fuse_read_spare(i) ||
>  			tegra_fuse_read_spare(i + CPU_SPEEDO_REDUND_OFFS);
>  		val = (val << 1) | (reg & 0x1);
>  	}
> @@ -84,7 +84,7 @@ void __init tegra20_init_speedo_data(struct tegra_sku_info *sku_info)
>  
>  	val = 0;
>  	for (i = SOC_SPEEDO_MSBIT; i >= SOC_SPEEDO_LSBIT; i--) {
> -		reg = tegra_fuse_read_spare(i) |
> +		reg = tegra_fuse_read_spare(i) ||
>  			tegra_fuse_read_spare(i + SOC_SPEEDO_REDUND_OFFS);
>  		val = (val << 1) | (reg & 0x1);
>  	}

It does seem correct, but nevertheless the code looks suspicious. reg is
already masked with 0x1 as far as I can tell, and there are other places
which depend on this (like speedo-tegra210.c). Guessing from the use of
tegra_fuse_read_spare() I would recommend changing its return type as it
is returing a bit value, not necessarily semantically a boolean.

Best Regards
Michał Mirosław