From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E7F3C433F5 for ; Tue, 26 Oct 2021 18:27:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6495860720 for ; Tue, 26 Oct 2021 18:27:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238304AbhJZSaT (ORCPT ); Tue, 26 Oct 2021 14:30:19 -0400 Received: from mail-ot1-f49.google.com ([209.85.210.49]:41723 "EHLO mail-ot1-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231530AbhJZSaI (ORCPT ); Tue, 26 Oct 2021 14:30:08 -0400 Received: by mail-ot1-f49.google.com with SMTP id v2-20020a05683018c200b0054e3acddd91so18550570ote.8; Tue, 26 Oct 2021 11:27:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=eFp4CK/cIp2DpF9Nk6vMYc4k/uaKBP5Bf1YLZsAxfy8=; b=00NkxEJKPSGLo7KVpbXcVHThJAGIjZf0j6sV2wvSbse8/G3VehtBvhTC1fV/PTpFn5 SzNQTElO05kGwFWbIbj88upTYdqdJDr3+bYVRsHBfq/9rfNIdYtaG8kcqoaFpmKLwc+d O4In8eDkTlFHYZ7gKHfw6p5nO8bhextz0F/ZHpnWQBNN/b8JUWJw+AfrFX8X+2lQ8C8l tehufxoh1vZ2XIBUzeXUg6m/O2GkN48j/0yzv0XNzUDcn8xqej5jroWVSyGh2uwwIBPZ GFcjs8RxW6nmsc+NmaWr2icTIKCZfqB6c6BK8koY93jA14aqFOk/U+julh4rh+EIVjYa H+Qw== X-Gm-Message-State: AOAM531wBYYC+S8gKtAGXxfcMukTsAsA9OBVLovnIPxhRzeIC3FBrDla 36UGqVIrLc/ePuZYGE6RCYsjdX5GtA== X-Google-Smtp-Source: ABdhPJwAI3IRkPjjJ3d2IqWje3ojRvX5pfch4KRIpOaHwTTrfF7i8XPhD1CUStoVg+jiE/yJp6STeA== X-Received: by 2002:a9d:6c8b:: with SMTP id c11mr4829768otr.50.1635272863827; Tue, 26 Oct 2021 11:27:43 -0700 (PDT) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id w9sm4701797otp.64.2021.10.26.11.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 11:27:43 -0700 (PDT) Received: (nullmailer pid 2979460 invoked by uid 1000); Tue, 26 Oct 2021 18:27:41 -0000 Date: Tue, 26 Oct 2021 13:27:41 -0500 From: Rob Herring To: Hector Martin Cc: linux-arm-kernel@lists.infradead.org, Marc Zyngier , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , Johan Hovold , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, Mark Kettenis Subject: Re: [PATCH v2 3/8] dt-bindings: power: Add apple,pmgr-pwrstate binding Message-ID: References: <20211025144718.157794-1-marcan@marcan.st> <20211025144718.157794-4-marcan@marcan.st> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211025144718.157794-4-marcan@marcan.st> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 25, 2021 at 11:47:13PM +0900, Hector Martin wrote: > This syscon child node represents a single SoC device controlled by the > PMGR block. This layout allows us to declare all device power state > controls (power/clock gating and reset) in the device tree, including > dependencies, instead of hardcoding it into the driver. The register > layout is uniform. > > Each pmgr-pwrstate node provides genpd and reset features, to be > consumed by downstream device nodes. > > Future SoCs are expected to use backwards compatible registers, and the > "apple,pmgr-pwrstate" represents any such interfaces (possibly with > additional features gated by the more specific compatible), allowing > them to be bound without driver updates. If a backwards incompatible > change is introduced in future SoCs, it will require a new compatible, > such as "apple,pmgr-pwrstate-v2". > > Reviewed-by: Mark Kettenis > Signed-off-by: Hector Martin > --- > .../bindings/power/apple,pmgr-pwrstate.yaml | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml > > diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml > new file mode 100644 > index 000000000000..010f8b641304 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Apple SoC PMGR Power States > + > +maintainers: > + - Hector Martin > + > +allOf: > + - $ref: "power-domain.yaml#" > + > +description: | > + Apple SoCs include a PMGR block responsible for power management, > + which can control various clocks, resets, power states, and > + performance features. This binding describes the device power > + state registers, which control power states and resets. > + > + Each instance of a power controller within the PMGR syscon node > + represents a generic power domain provider, as documented in > + Documentation/devicetree/bindings/power/power-domain.yaml. > + The provider controls a single SoC block. The power hierarchy is > + represented via power-domains relationships between these nodes. > + > + See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml > + for the top-level PMGR node documentation. > + > +properties: > + compatible: > + items: > + - enum: > + - apple,t8103-pmgr-pwrstate > + - const: apple,pmgr-pwrstate > + > + reg: > + maxItems: 1 > + > + "#power-domain-cells": > + const: 0 > + > + "#reset-cells": > + const: 0 > + > + power-domains: > + description: > + Reference to parent power domains. A domain may have multiple parents, > + and all will be powered up when it is powered. > + minItems: 1 > + > + label: > + description: | > + Specifies the name of the SoC domain being controlled. This is used to > + name the power/reset domains. > + > + apple,always-on: > + description: | Can drop '|' on these too. Otherwise, Reviewed-by: Rob Herring > + Forces this power domain to always be powered up. > + type: boolean > + > +required: > + - compatible > + - reg > + - "#power-domain-cells" > + - "#reset-cells" > + - label > + > +additionalProperties: false > -- > 2.33.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5298CC433F5 for ; Tue, 26 Oct 2021 18:29:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 20F6C60F9D for ; Tue, 26 Oct 2021 18:29:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 20F6C60F9D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fPGLEewmvZtdEdI79ZufhjMSnWB2WiNECqelgkOSO58=; b=TRtbFlm3dz8d0M Pk7haYcCz1ccs7jERBQkkQl6ROqy4QSY20SGASMF1Zt4kEJz0b0NTLztZ8hhtAHmnYLXaZVEpoCfI Cmue30yt2vNEKSqYY/xsUehrB6j04njo+v8OcLmMkFII6RYfZaQJ6iDg+84TobO0QrhHq3cACpFSq 5hyvTce58lzb/4eRwN5gsfnqqszfIeS/+T1ET2UG64f436y0omULqPEDfUwxxTJM9jYN45dUrlE1x GWEEA5HvPqgnC09sqhNYLgLkvo4IOIqMojUqYvreNhR7+rXnrEeNO2PwwEgtktaXu8A6Pvo4YUric +JmuD9UV7ob9pCvvvgYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mfRAr-002lHh-9I; Tue, 26 Oct 2021 18:27:49 +0000 Received: from mail-ot1-f44.google.com ([209.85.210.44]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mfRAn-002lG8-AS for linux-arm-kernel@lists.infradead.org; Tue, 26 Oct 2021 18:27:46 +0000 Received: by mail-ot1-f44.google.com with SMTP id d21-20020a9d4f15000000b0054e677e0ac5so21029666otl.11 for ; Tue, 26 Oct 2021 11:27:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=eFp4CK/cIp2DpF9Nk6vMYc4k/uaKBP5Bf1YLZsAxfy8=; b=KEOqpI0+2X9ftkaOFMAJlhL9DFuD/fr6eyUcMmFE1792/91lZ2kEPncEftKcZfYc9P J76W3fGwb9BmktsZEyz/IFBOW4lMkLzBqeJdrAIG/2703oPRLUouutjgsZbdGq6LBQ41 Ihsh7OlFNFb+mu7wThOPY1EnZJwagYzrHqepHrSYrFNG3CfCpDpfE4B3dfj9/UAV6t2r mIRMBObWb+qhRqPtMkJ3UPr2oblhJ+KU6srg/ncDrH5CBMmetMyba2HQqB+vbyghLNEM xu+EbbfY8u4P7P3XUhzl7G2LZmwPI3EpqqHXRpn3MDxyGNnwYeKkvUoXQd8QxxNfQfkk CO/Q== X-Gm-Message-State: AOAM533qrAxmElFJE1HHqNmw+9V3fqbmrAAhmEnXB4wQ49IrBBF5EXju 18VVa9zXgRntHEnhhVd0Qw== X-Google-Smtp-Source: ABdhPJwAI3IRkPjjJ3d2IqWje3ojRvX5pfch4KRIpOaHwTTrfF7i8XPhD1CUStoVg+jiE/yJp6STeA== X-Received: by 2002:a9d:6c8b:: with SMTP id c11mr4829768otr.50.1635272863827; Tue, 26 Oct 2021 11:27:43 -0700 (PDT) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id w9sm4701797otp.64.2021.10.26.11.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 11:27:43 -0700 (PDT) Received: (nullmailer pid 2979460 invoked by uid 1000); Tue, 26 Oct 2021 18:27:41 -0000 Date: Tue, 26 Oct 2021 13:27:41 -0500 From: Rob Herring To: Hector Martin Cc: linux-arm-kernel@lists.infradead.org, Marc Zyngier , Arnd Bergmann , Linus Walleij , Alyssa Rosenzweig , Krzysztof Kozlowski , Greg Kroah-Hartman , Mark Kettenis , Philipp Zabel , "Rafael J. Wysocki" , Johan Hovold , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, Mark Kettenis Subject: Re: [PATCH v2 3/8] dt-bindings: power: Add apple,pmgr-pwrstate binding Message-ID: References: <20211025144718.157794-1-marcan@marcan.st> <20211025144718.157794-4-marcan@marcan.st> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211025144718.157794-4-marcan@marcan.st> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211026_112745_408936_50DDDB19 X-CRM114-Status: GOOD ( 28.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Oct 25, 2021 at 11:47:13PM +0900, Hector Martin wrote: > This syscon child node represents a single SoC device controlled by the > PMGR block. This layout allows us to declare all device power state > controls (power/clock gating and reset) in the device tree, including > dependencies, instead of hardcoding it into the driver. The register > layout is uniform. > > Each pmgr-pwrstate node provides genpd and reset features, to be > consumed by downstream device nodes. > > Future SoCs are expected to use backwards compatible registers, and the > "apple,pmgr-pwrstate" represents any such interfaces (possibly with > additional features gated by the more specific compatible), allowing > them to be bound without driver updates. If a backwards incompatible > change is introduced in future SoCs, it will require a new compatible, > such as "apple,pmgr-pwrstate-v2". > > Reviewed-by: Mark Kettenis > Signed-off-by: Hector Martin > --- > .../bindings/power/apple,pmgr-pwrstate.yaml | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml > > diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml > new file mode 100644 > index 000000000000..010f8b641304 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml > @@ -0,0 +1,69 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Apple SoC PMGR Power States > + > +maintainers: > + - Hector Martin > + > +allOf: > + - $ref: "power-domain.yaml#" > + > +description: | > + Apple SoCs include a PMGR block responsible for power management, > + which can control various clocks, resets, power states, and > + performance features. This binding describes the device power > + state registers, which control power states and resets. > + > + Each instance of a power controller within the PMGR syscon node > + represents a generic power domain provider, as documented in > + Documentation/devicetree/bindings/power/power-domain.yaml. > + The provider controls a single SoC block. The power hierarchy is > + represented via power-domains relationships between these nodes. > + > + See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml > + for the top-level PMGR node documentation. > + > +properties: > + compatible: > + items: > + - enum: > + - apple,t8103-pmgr-pwrstate > + - const: apple,pmgr-pwrstate > + > + reg: > + maxItems: 1 > + > + "#power-domain-cells": > + const: 0 > + > + "#reset-cells": > + const: 0 > + > + power-domains: > + description: > + Reference to parent power domains. A domain may have multiple parents, > + and all will be powered up when it is powered. > + minItems: 1 > + > + label: > + description: | > + Specifies the name of the SoC domain being controlled. This is used to > + name the power/reset domains. > + > + apple,always-on: > + description: | Can drop '|' on these too. Otherwise, Reviewed-by: Rob Herring > + Forces this power domain to always be powered up. > + type: boolean > + > +required: > + - compatible > + - reg > + - "#power-domain-cells" > + - "#reset-cells" > + - label > + > +additionalProperties: false > -- > 2.33.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel