From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CF39C433F5 for ; Tue, 2 Nov 2021 21:09:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC48960F56 for ; Tue, 2 Nov 2021 21:09:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org CC48960F56 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 45351737F6; Tue, 2 Nov 2021 21:09:01 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 70740737F6; Tue, 2 Nov 2021 21:08:59 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10156"; a="218276994" X-IronPort-AV: E=Sophos;i="5.87,203,1631602800"; d="scan'208";a="218276994" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2021 14:08:58 -0700 X-IronPort-AV: E=Sophos;i="5.87,203,1631602800"; d="scan'208";a="500757180" Received: from lvillalo-mobl1.amr.corp.intel.com (HELO intel.com) ([10.249.32.130]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2021 14:08:57 -0700 Date: Tue, 2 Nov 2021 22:08:54 +0100 From: Andi Shyti To: Tvrtko Ursulin Subject: Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts Message-ID: References: <20211029032817.3747750-1-matthew.d.roper@intel.com> <20211029032817.3747750-6-matthew.d.roper@intel.com> <8c2ec510-4e86-97f1-f0a9-872a2168455d@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8c2ec510-4e86-97f1-f0a9-872a2168455d@linux.intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Andi Shyti Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Tvrtko, > > > > [...] > > > > > > > > > static int > > > > > intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr) > > > > > > > > we don't actually need 'id', it's gt->info.id. It's introduced in > > > > patch 3 with the value '0' but it's not needed. > > > > > > I have a suspicion code got munged up over endless rebases and refactors. > > > > > > This patch is the one which introduces the id member to gt->info. But it is not setting it, even though I suspect the intent was for intel_gt_tile_setup to do that. > > > > > > Instead gt->info.id is only set to a valid value in last patch of this series inside intel_gt_probe_all: > > > > > > + gt->i915 = i915; > > > + gt->name = gtdef->name; > > > + gt->type = gtdef->type; > > > + gt->info.engine_mask = gtdef->engine_mask; > > > + gt->info.id = i; > > > + > > > + drm_dbg(&i915->drm, "Setting up %s %u\n", gt->name, gt->info.id); > > > + ret = intel_gt_tile_setup(gt, i, phys_addr + gtdef->mapping_base); > > > > > > And intel_gt_tile_setup then calls __intel_gt_init_early which assigns gt->i915 yet again. > > > > > > So I'd say there is probably space to bring this all into a more streamlined flow, even more than what you suggest below. > > > > yes, I noticed them! > > > > Patch 3, 5 and 10 are very much connected with each other: 3 > > prepares for one tile, 5 prepares for multitile and 10 does the > > multitile. While in between other patches are doing other things. > > > > On top of some cleanups we could also rearrange the patches with > > some squashing and reordering to have them a bit more linear and > > also easier to review. > > Yes. Maybe make intel_gt_tile_setup accept more arguments so it can be truly > used to setup a gt? > > intel_gt_tile_setup(gt, id, name, type, engine_mask) > > The usual thing where patch which adds something extends the prototype to > include more stuff. If that applies here. > > I know it is originally my patch but I don't have the time to rework it, > much less the whole series, so usual dispensation to take over authorship if > changes are large applies. as no one is stepping forward, if you and Matt are OK, I can try to venture in some refactoring of these three patches (3, 5 and 10). Andi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 961C4C433EF for ; Tue, 2 Nov 2021 21:09:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5047A61051 for ; Tue, 2 Nov 2021 21:09:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5047A61051 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E261737F7; Tue, 2 Nov 2021 21:09:01 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 70740737F6; Tue, 2 Nov 2021 21:08:59 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10156"; a="218276994" X-IronPort-AV: E=Sophos;i="5.87,203,1631602800"; d="scan'208";a="218276994" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2021 14:08:58 -0700 X-IronPort-AV: E=Sophos;i="5.87,203,1631602800"; d="scan'208";a="500757180" Received: from lvillalo-mobl1.amr.corp.intel.com (HELO intel.com) ([10.249.32.130]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2021 14:08:57 -0700 Date: Tue, 2 Nov 2021 22:08:54 +0100 From: Andi Shyti To: Tvrtko Ursulin Message-ID: References: <20211029032817.3747750-1-matthew.d.roper@intel.com> <20211029032817.3747750-6-matthew.d.roper@intel.com> <8c2ec510-4e86-97f1-f0a9-872a2168455d@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8c2ec510-4e86-97f1-f0a9-872a2168455d@linux.intel.com> Subject: Re: [Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Tvrtko, > > > > [...] > > > > > > > > > static int > > > > > intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr) > > > > > > > > we don't actually need 'id', it's gt->info.id. It's introduced in > > > > patch 3 with the value '0' but it's not needed. > > > > > > I have a suspicion code got munged up over endless rebases and refactors. > > > > > > This patch is the one which introduces the id member to gt->info. But it is not setting it, even though I suspect the intent was for intel_gt_tile_setup to do that. > > > > > > Instead gt->info.id is only set to a valid value in last patch of this series inside intel_gt_probe_all: > > > > > > + gt->i915 = i915; > > > + gt->name = gtdef->name; > > > + gt->type = gtdef->type; > > > + gt->info.engine_mask = gtdef->engine_mask; > > > + gt->info.id = i; > > > + > > > + drm_dbg(&i915->drm, "Setting up %s %u\n", gt->name, gt->info.id); > > > + ret = intel_gt_tile_setup(gt, i, phys_addr + gtdef->mapping_base); > > > > > > And intel_gt_tile_setup then calls __intel_gt_init_early which assigns gt->i915 yet again. > > > > > > So I'd say there is probably space to bring this all into a more streamlined flow, even more than what you suggest below. > > > > yes, I noticed them! > > > > Patch 3, 5 and 10 are very much connected with each other: 3 > > prepares for one tile, 5 prepares for multitile and 10 does the > > multitile. While in between other patches are doing other things. > > > > On top of some cleanups we could also rearrange the patches with > > some squashing and reordering to have them a bit more linear and > > also easier to review. > > Yes. Maybe make intel_gt_tile_setup accept more arguments so it can be truly > used to setup a gt? > > intel_gt_tile_setup(gt, id, name, type, engine_mask) > > The usual thing where patch which adds something extends the prototype to > include more stuff. If that applies here. > > I know it is originally my patch but I don't have the time to rework it, > much less the whole series, so usual dispensation to take over authorship if > changes are large applies. as no one is stepping forward, if you and Matt are OK, I can try to venture in some refactoring of these three patches (3, 5 and 10). Andi