From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6ED1C433F5 for ; Mon, 29 Nov 2021 16:57:36 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 127174B173; Mon, 29 Nov 2021 11:57:36 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xIlgyhdB3QTT; Mon, 29 Nov 2021 11:57:34 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 49B2D4B199; Mon, 29 Nov 2021 11:57:34 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B28E94B17B for ; Mon, 29 Nov 2021 11:57:32 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BptX-a4U4iXy for ; Mon, 29 Nov 2021 11:57:31 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3C7AA4B173 for ; Mon, 29 Nov 2021 11:57:31 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A0371063; Mon, 29 Nov 2021 08:57:30 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B16303F5A1; Mon, 29 Nov 2021 08:57:28 -0800 (PST) Date: Mon, 29 Nov 2021 16:59:21 +0000 From: Alexandru Elisei To: Marc Zyngier Subject: Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU Message-ID: References: <20211126115533.217903-1-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211126115533.217903-1-maz@kernel.org> Cc: kvm@vger.kernel.org, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, Tested on FVP and the nasty splat goes away, so it works for me: Tested-by: Alexandru Elisei The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the bit behave as RES0, which is the architectural value for the field when FEAT_PMUv3p7 is absent. So the patch looks correct to me: Reviewed-by: Alexandru Elisei Thanks, Alex On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote: > When running a KVM guest hosted on an ARMv8.7 machine, the host > kernel complains that it doesn't know about the architected number > of events. > > Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kvm/pmu-emul.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index cdb590840b3f..5de90138d0a4 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -1036,6 +1036,7 @@ > #define ID_AA64DFR0_PMUVER_8_1 0x4 > #define ID_AA64DFR0_PMUVER_8_4 0x5 > #define ID_AA64DFR0_PMUVER_8_5 0x6 > +#define ID_AA64DFR0_PMUVER_8_7 0x7 > #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf > > #define ID_AA64DFR0_PMSVER_8_2 0x1 > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index a5e4bbf5e68f..ca92cc5c71c6 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) > case ID_AA64DFR0_PMUVER_8_1: > case ID_AA64DFR0_PMUVER_8_4: > case ID_AA64DFR0_PMUVER_8_5: > + case ID_AA64DFR0_PMUVER_8_7: > return GENMASK(15, 0); > default: /* Shouldn't be here, just for sanity */ > WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver); > -- > 2.30.2 > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F8A7C433EF for ; Mon, 29 Nov 2021 16:58:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=70RmNLidAKi20lVeEXtem4Icb5Z1HJjr9DWhUztt31M=; b=hJC8nj0GStvpCF Z9NG5yZDrEeu+F92ckZL1AzBGGQTah3hLtEI/ob9yoKnpkNq3xbvNm7Ha0XYeHf2wQaCc+MA8UXkX 0+4bMj1esB0kJXnnAv0VUrN1ddAahbI4mbCWVwi9P0r6+7pWvgtUNMhu9cJtj+AzU7DQeeaKIsNep BxtC0Y3PUIAN2jFAjr6hKZST9DViY9DSejdwVleGO0Kea2ktxnxYiF8JDx1olBnsijfthYKZu6h+E w/PdPvuDRtZCde62CRKOSuf8GHG3h323U7TY+ZE+ilqwkaZXwZKcQ43ofnpvHPNASWH6Oqd3BfcPL rLL2ao2CPyvrXlhbGbWg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrjyD-001Wb4-3B; Mon, 29 Nov 2021 16:57:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrjy9-001Wa5-EC for linux-arm-kernel@lists.infradead.org; Mon, 29 Nov 2021 16:57:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A0371063; Mon, 29 Nov 2021 08:57:30 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B16303F5A1; Mon, 29 Nov 2021 08:57:28 -0800 (PST) Date: Mon, 29 Nov 2021 16:59:21 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , kernel-team@android.com Subject: Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU Message-ID: References: <20211126115533.217903-1-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211126115533.217903-1-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211129_085733_574617_F449B2FA X-CRM114-Status: GOOD ( 19.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, Tested on FVP and the nasty splat goes away, so it works for me: Tested-by: Alexandru Elisei The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the bit behave as RES0, which is the architectural value for the field when FEAT_PMUv3p7 is absent. So the patch looks correct to me: Reviewed-by: Alexandru Elisei Thanks, Alex On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote: > When running a KVM guest hosted on an ARMv8.7 machine, the host > kernel complains that it doesn't know about the architected number > of events. > > Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kvm/pmu-emul.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index cdb590840b3f..5de90138d0a4 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -1036,6 +1036,7 @@ > #define ID_AA64DFR0_PMUVER_8_1 0x4 > #define ID_AA64DFR0_PMUVER_8_4 0x5 > #define ID_AA64DFR0_PMUVER_8_5 0x6 > +#define ID_AA64DFR0_PMUVER_8_7 0x7 > #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf > > #define ID_AA64DFR0_PMSVER_8_2 0x1 > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index a5e4bbf5e68f..ca92cc5c71c6 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) > case ID_AA64DFR0_PMUVER_8_1: > case ID_AA64DFR0_PMUVER_8_4: > case ID_AA64DFR0_PMUVER_8_5: > + case ID_AA64DFR0_PMUVER_8_7: > return GENMASK(15, 0); > default: /* Shouldn't be here, just for sanity */ > WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver); > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 948F9C433EF for ; Mon, 29 Nov 2021 16:59:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347466AbhK2RCt (ORCPT ); Mon, 29 Nov 2021 12:02:49 -0500 Received: from foss.arm.com ([217.140.110.172]:43604 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346849AbhK2RAs (ORCPT ); Mon, 29 Nov 2021 12:00:48 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A0371063; Mon, 29 Nov 2021 08:57:30 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B16303F5A1; Mon, 29 Nov 2021 08:57:28 -0800 (PST) Date: Mon, 29 Nov 2021 16:59:21 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , kernel-team@android.com Subject: Re: [PATCH] KVM: arm64: Add minimal handling for the ARMv8.7 PMU Message-ID: References: <20211126115533.217903-1-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211126115533.217903-1-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Marc, Tested on FVP and the nasty splat goes away, so it works for me: Tested-by: Alexandru Elisei The guest visible PMCR_EL0.FZ0 bit added by FEAT_PMUv3p7 is cleared on register reset/write because ARMV8_PMU_PMCR_MASK is 0xff. This makes the bit behave as RES0, which is the architectural value for the field when FEAT_PMUv3p7 is absent. So the patch looks correct to me: Reviewed-by: Alexandru Elisei Thanks, Alex On Fri, Nov 26, 2021 at 11:55:33AM +0000, Marc Zyngier wrote: > When running a KVM guest hosted on an ARMv8.7 machine, the host > kernel complains that it doesn't know about the architected number > of events. > > Fix it by adding the PMUver code corresponding to PMUv3 for ARMv8.7. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/sysreg.h | 1 + > arch/arm64/kvm/pmu-emul.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index cdb590840b3f..5de90138d0a4 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -1036,6 +1036,7 @@ > #define ID_AA64DFR0_PMUVER_8_1 0x4 > #define ID_AA64DFR0_PMUVER_8_4 0x5 > #define ID_AA64DFR0_PMUVER_8_5 0x6 > +#define ID_AA64DFR0_PMUVER_8_7 0x7 > #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf > > #define ID_AA64DFR0_PMSVER_8_2 0x1 > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index a5e4bbf5e68f..ca92cc5c71c6 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -28,6 +28,7 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) > case ID_AA64DFR0_PMUVER_8_1: > case ID_AA64DFR0_PMUVER_8_4: > case ID_AA64DFR0_PMUVER_8_5: > + case ID_AA64DFR0_PMUVER_8_7: > return GENMASK(15, 0); > default: /* Shouldn't be here, just for sanity */ > WARN_ONCE(1, "Unknown PMU version %d\n", kvm->arch.pmuver); > -- > 2.30.2 >