From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 916A2C433F5 for ; Fri, 10 Dec 2021 18:16:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236984AbhLJSU1 (ORCPT ); Fri, 10 Dec 2021 13:20:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236861AbhLJSU0 (ORCPT ); Fri, 10 Dec 2021 13:20:26 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 594D6C061746; Fri, 10 Dec 2021 10:16:51 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 1E5F0B8294F; Fri, 10 Dec 2021 18:16:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16AB2C00446; Fri, 10 Dec 2021 18:16:46 +0000 (UTC) Date: Fri, 10 Dec 2021 18:16:43 +0000 From: Catalin Marinas To: Sai Prakash Ranjan Cc: Will Deacon , Marc Zyngier , Arnd Bergmann , Steven Rostedt , gregkh , quic_psodagud@quicinc.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCHv6 1/5] arm64: io: Use asm-generic high level MMIO accessors Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Dec 07, 2021 at 12:24:45PM +0530, Sai Prakash Ranjan wrote: > Remove custom arm64 MMIO accessors read{b,w,l,q} and their relaxed > versions in support to use asm-generic defined accessors. Also define > one set of IO barriers (ar/bw version) used by asm-generic code to > override the arm64 specific variants. > > Suggested-by: Arnd Bergmann > Signed-off-by: Sai Prakash Ranjan > --- > arch/arm64/include/asm/io.h | 41 ++++++++----------------------------- > 1 file changed, 8 insertions(+), 33 deletions(-) > > diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h > index 7fd836bea7eb..1b436810d779 100644 > --- a/arch/arm64/include/asm/io.h > +++ b/arch/arm64/include/asm/io.h > @@ -91,7 +91,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) > } > > /* IO barriers */ > -#define __iormb(v) \ > +#define __io_ar(v) \ > ({ \ > unsigned long tmp; \ > \ > @@ -108,39 +108,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) > : "memory"); \ > }) > > -#define __io_par(v) __iormb(v) > -#define __iowmb() dma_wmb() > -#define __iomb() dma_mb() > - > -/* > - * Relaxed I/O memory access primitives. These follow the Device memory > - * ordering rules but do not guarantee any ordering relative to Normal memory > - * accesses. > - */ > -#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) > -#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) > -#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) > -#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) > +#define __io_bw() dma_wmb() > +#define __io_br(v) > +#define __io_aw(v) > > -#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) > -#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) > -#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) > -#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) > - > -/* > - * I/O memory access primitives. Reads are ordered relative to any > - * following Normal memory access. Writes are ordered relative to any prior > - * Normal memory access. > - */ > -#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; }) > -#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; }) > -#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) > -#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; }) > - > -#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) > -#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) > -#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) > -#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) > +/* arm64-specific, don't use in portable drivers */ > +#define __iormb(v) __io_ar(v) > +#define __iowmb() __io_bw() > +#define __iomb() dma_mb() More of a nitpick but I'd keep the __iormb()/__iowmb() as they currently are and just define the generic __io_ar() etc. in terms of the former. -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33969C433F5 for ; Fri, 10 Dec 2021 18:18:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aymIVn9UGQ4KkxmVBjaURa/UgJRwd6D8aumVMFHq4nw=; b=uK/d/gRf5E+z5Q dnECU+PgYp8SUsOzv8rr8ja8N5OLY1wZfTWUmSCAqJ2BkT2N4lcpLZsIz2LBQP1hC0oMxetEQ/iGl ZtcAvX0j1bRNNDvvjjc27fYs9FTJ3oRhKbJSuam7q8t4sAGMLy5EskdVY1vTX3a7os2wiBS0iIT/k ppH4uXOdYDg0zi1pTIKJQfWqZv6qBOMzDt31D4WzU6awvfOlYZ5Wka6tszrWqXZUNZ0e+BHTRrMpX 6aBc1gps1GP9NyrsqFJZ7u00fXqWaFqacTY7qNfRiShCB71o50MaNyZ5I2lZW/zuOK8rULkKxef9B 1Iwo8k2JucO894tMFTew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvkS3-003Aro-GN; Fri, 10 Dec 2021 18:16:59 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvkRw-003Apw-BH for linux-arm-kernel@lists.infradead.org; Fri, 10 Dec 2021 18:16:57 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id AF420CE2BCA; Fri, 10 Dec 2021 18:16:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16AB2C00446; Fri, 10 Dec 2021 18:16:46 +0000 (UTC) Date: Fri, 10 Dec 2021 18:16:43 +0000 From: Catalin Marinas To: Sai Prakash Ranjan Cc: Will Deacon , Marc Zyngier , Arnd Bergmann , Steven Rostedt , gregkh , quic_psodagud@quicinc.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCHv6 1/5] arm64: io: Use asm-generic high level MMIO accessors Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211210_101652_798841_D0EF210A X-CRM114-Status: GOOD ( 17.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 07, 2021 at 12:24:45PM +0530, Sai Prakash Ranjan wrote: > Remove custom arm64 MMIO accessors read{b,w,l,q} and their relaxed > versions in support to use asm-generic defined accessors. Also define > one set of IO barriers (ar/bw version) used by asm-generic code to > override the arm64 specific variants. > > Suggested-by: Arnd Bergmann > Signed-off-by: Sai Prakash Ranjan > --- > arch/arm64/include/asm/io.h | 41 ++++++++----------------------------- > 1 file changed, 8 insertions(+), 33 deletions(-) > > diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h > index 7fd836bea7eb..1b436810d779 100644 > --- a/arch/arm64/include/asm/io.h > +++ b/arch/arm64/include/asm/io.h > @@ -91,7 +91,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) > } > > /* IO barriers */ > -#define __iormb(v) \ > +#define __io_ar(v) \ > ({ \ > unsigned long tmp; \ > \ > @@ -108,39 +108,14 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) > : "memory"); \ > }) > > -#define __io_par(v) __iormb(v) > -#define __iowmb() dma_wmb() > -#define __iomb() dma_mb() > - > -/* > - * Relaxed I/O memory access primitives. These follow the Device memory > - * ordering rules but do not guarantee any ordering relative to Normal memory > - * accesses. > - */ > -#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) > -#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) > -#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) > -#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) > +#define __io_bw() dma_wmb() > +#define __io_br(v) > +#define __io_aw(v) > > -#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) > -#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) > -#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) > -#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) > - > -/* > - * I/O memory access primitives. Reads are ordered relative to any > - * following Normal memory access. Writes are ordered relative to any prior > - * Normal memory access. > - */ > -#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; }) > -#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; }) > -#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) > -#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; }) > - > -#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) > -#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) > -#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) > -#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) > +/* arm64-specific, don't use in portable drivers */ > +#define __iormb(v) __io_ar(v) > +#define __iowmb() __io_bw() > +#define __iomb() dma_mb() More of a nitpick but I'd keep the __iormb()/__iowmb() as they currently are and just define the generic __io_ar() etc. in terms of the former. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel