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From: "Guido Günther" <agx@sigxcpu.org>
To: Lucas Stach <dev@lynxeye.de>
Cc: Shawn Guo <shawnguo@kernel.org>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Martin Kepplinger <martink@posteo.de>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: dts: imx8mq: disable DDRC node by default
Date: Mon, 13 Dec 2021 09:34:18 +0100	[thread overview]
Message-ID: <YbcFikbUjZFIoy/e@qwark.sigxcpu.org> (raw)
In-Reply-To: <20211212191541.2148178-1-dev@lynxeye.de>

Hi,
On Sun, Dec 12, 2021 at 08:15:41PM +0100, Lucas Stach wrote:
> Without a OPP table or a downstream TF-A running on the system the DDRC will
> fail to probe, as it has no means to scale the DRAM frequency in that case.
> This however will block the bus scaling driver to come up and this in turn
> prevents other devices that hook into the interconnect from probing.
> 
> If the DDRC is disabled, the interconnect driver will simply ignore it. As
> most systems don't want to scale the DRAM frequency, disable the node by
> default and only enable it on the systems that actually uses this
> capability and provides a valid OPP table in the DT.
> 
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
>  arch/arm64/boot/dts/freescale/imx8mq-evk.dts      | 1 +
>  arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 +
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi         | 1 +
>  3 files changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index b83df77195ec..e989a9e450ed 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -122,6 +122,7 @@ &A53_3 {
>  };
>  
>  &ddrc {
> +	status = "okay";
>  	operating-points-v2 = <&ddrc_opp_table>;
>  
>  	ddrc_opp_table: opp-table {
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
> index 60d47c71499b..5c0e98c36f94 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
> @@ -238,6 +238,7 @@ &A53_3 {
>  };
>  
>  &ddrc {
> +	status = "okay";
>  	operating-points-v2 = <&ddrc_opp_table>;
>  
>  	ddrc_opp_table: opp-table {
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 972766b67a15..f5af9765e239 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1554,6 +1554,7 @@ ddrc: memory-controller@3d400000 {
>  				 <&clk IMX8MQ_DRAM_PLL_OUT>,
>  				 <&clk IMX8MQ_CLK_DRAM_ALT>,
>  				 <&clk IMX8MQ_CLK_DRAM_APB>;
> +			status = "disabled";
>  		};
>  
>  		ddr-pmu@3d800000 {

Reviewed-by: Guido Günther <agx@sigxcpu.org>

Cheers,
 -- Guido

> -- 
> 2.31.1
> 

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  parent reply	other threads:[~2021-12-13  8:44 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-12 19:15 [PATCH] arm64: dts: imx8mq: disable DDRC node by default Lucas Stach
2021-12-12 19:29 ` Fabio Estevam
2021-12-13 14:36   ` Lucas Stach
2021-12-13  8:31 ` Martin Kepplinger
2021-12-13  8:34 ` Guido Günther [this message]
2021-12-16  5:58 ` Shawn Guo

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