From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6F46C433EF for ; Tue, 14 Dec 2021 12:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233757AbhLNMCi (ORCPT ); Tue, 14 Dec 2021 07:02:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229525AbhLNMCg (ORCPT ); Tue, 14 Dec 2021 07:02:36 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13538C061574; Tue, 14 Dec 2021 04:02:36 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A2EE3614A6; Tue, 14 Dec 2021 12:02:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CAB6C34601; Tue, 14 Dec 2021 12:02:30 +0000 (UTC) Date: Tue, 14 Dec 2021 12:02:27 +0000 From: Catalin Marinas To: Yee Lee Cc: linux-kernel@vger.kernel.org, nicholas.Tang@mediatek.com, Kuan-Ying.lee@mediatek.com, chinwen.chang@mediatek.com, Jonathan Corbet , Will Deacon , Matthias Brugger , "Paul E. McKenney" , Randy Dunlap , Andrew Morton , Thomas Gleixner , "Maciej W. Rozycki" , Viresh Kumar , Peter Zijlstra , Vlastimil Babka , Marc Zyngier , David Brazdil , Ard Biesheuvel , Fuad Tabba , "open list:DOCUMENTATION" , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , "moderated list:ARM/Mediatek SoC support" Subject: Re: [PATCH v3 1/1] arm64/cpufeature: Optionally disable MTE via command-line Message-ID: References: <20210730144957.30938-1-yee.lee@mediatek.com> <20210730144957.30938-2-yee.lee@mediatek.com> <20210802153036.GH18685@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Dec 14, 2021 at 04:19:05PM +0800, Yee Lee wrote: > On Fri, 2021-12-03 at 16:33 +0000, Catalin Marinas wrote: > > On Thu, Nov 25, 2021 at 06:19:29PM +0800, Yee Lee wrote: > > > As pointed out earlier, the hardware has been verified that still has > > > transaction sending to DRAM due to mair_el1(Normal_tagged) is > > > setup. That means the override in this patch would be incompleted and > > > cannot achieve to avoid undesired hardware confliction by disabling MTE. > > > > > > Do we have other options to delay the configuration on MAIR_EL1 after > > > the override? Or maybe another CONFIG to bypass the init in __cpu_setup? > > > > This register is trickier as it may be cached in the TLB (IIRC). I think > > deferring the setting of SCTLR_EL1.ATA(0) should be sufficient. Can you > > try the diff I sent in the previous email and confirm that the accesses > > to the allocation tag storage are blocked? > > Yes, the previous diff is already online. > > In our experiment, with cmdline, "arm64.nomte", cpu_enable_mte() is > bypassed and the ATA0 is not set, but the access to tag memory still > dispatches. Only as MAIR_EL1 remains MAIR_ATTR_NORMAL, instead of > MAIR_ATTR_NORMAL_TAGGED, the access will stop. > > From the manual, I think ATA only affects TAG instructions like STG, > IRG, but not the tag access within normal STR/LDR. The ARM ARM states SCTLR_EL1.ATA0 == 0 means "access to allocation tags is prevented". The AArch64.MemSingle[] pseudocode ends up with similar checks: https://developer.arm.com/documentation/ddi0596/2021-09/Shared-Pseudocode/AArch64-Functions?lang=en#AArch64.MemSingle.read.5 before reading the tags from memory in AArch64.CheckTag(): https://developer.arm.com/documentation/ddi0596/2021-09/Shared-Pseudocode/AArch64-Functions?lang=en#AArch64.CheckTag.4 My suggestion is to raise this with support@arm.com (feel free to cc me) so that we clarify the hardware behaviour. I don't think it's entirely correct (it's more like, is there a risk of external aborts caused by access to allocation tag storage that's not present?) -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E56B2C433EF for ; Tue, 14 Dec 2021 12:12:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ORmlxIQF4C0oz4xVfF01MOBOO23I/I9LrmT4x3+csBc=; b=I6LfZyCqQnbqCu JEskgCU2NuK1wp9cKTOTQqHf8aCy68Zj7wH+XlqAc8ztjGhPrIZKiO6c1dbKa9A9+1Ncm+jhxWLGC vCBTXveGbruxSq0zpv8tpfBWPgFL9qN2xS1S9aUKxa9JCaoXwMmSty0d1P0Q+/IUmqKJTVShZIiyh 2dbCCXSZqfukJeQhJYkM40Xj78ozPanCJfeypDcxhQytXciYMdEyR1r3ZDSqj/7FtJHClnGw7N5di pG3VO3W5vKba4HmUmkEPUCffuWyJVCkzElKAgYQzPl8WAjUoNlX03E7XMXgbLfkDMdK+JFLPHLvt/ L7HqCtSDkBGPMuCqUYRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx6fQ-00DrQA-Jr; Tue, 14 Dec 2021 12:12:24 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx6Vw-00DozJ-7L; Tue, 14 Dec 2021 12:02:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 97ABE614A2; Tue, 14 Dec 2021 12:02:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CAB6C34601; Tue, 14 Dec 2021 12:02:30 +0000 (UTC) Date: Tue, 14 Dec 2021 12:02:27 +0000 From: Catalin Marinas To: Yee Lee Cc: linux-kernel@vger.kernel.org, nicholas.Tang@mediatek.com, Kuan-Ying.lee@mediatek.com, chinwen.chang@mediatek.com, Jonathan Corbet , Will Deacon , Matthias Brugger , "Paul E. McKenney" , Randy Dunlap , Andrew Morton , Thomas Gleixner , "Maciej W. Rozycki" , Viresh Kumar , Peter Zijlstra , Vlastimil Babka , Marc Zyngier , David Brazdil , Ard Biesheuvel , Fuad Tabba , "open list:DOCUMENTATION" , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , "moderated list:ARM/Mediatek SoC support" Subject: Re: [PATCH v3 1/1] arm64/cpufeature: Optionally disable MTE via command-line Message-ID: References: <20210730144957.30938-1-yee.lee@mediatek.com> <20210730144957.30938-2-yee.lee@mediatek.com> <20210802153036.GH18685@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_040236_399193_726AED40 X-CRM114-Status: GOOD ( 25.66 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, Dec 14, 2021 at 04:19:05PM +0800, Yee Lee wrote: > On Fri, 2021-12-03 at 16:33 +0000, Catalin Marinas wrote: > > On Thu, Nov 25, 2021 at 06:19:29PM +0800, Yee Lee wrote: > > > As pointed out earlier, the hardware has been verified that still has > > > transaction sending to DRAM due to mair_el1(Normal_tagged) is > > > setup. That means the override in this patch would be incompleted and > > > cannot achieve to avoid undesired hardware confliction by disabling MTE. > > > > > > Do we have other options to delay the configuration on MAIR_EL1 after > > > the override? Or maybe another CONFIG to bypass the init in __cpu_setup? > > > > This register is trickier as it may be cached in the TLB (IIRC). I think > > deferring the setting of SCTLR_EL1.ATA(0) should be sufficient. Can you > > try the diff I sent in the previous email and confirm that the accesses > > to the allocation tag storage are blocked? > > Yes, the previous diff is already online. > > In our experiment, with cmdline, "arm64.nomte", cpu_enable_mte() is > bypassed and the ATA0 is not set, but the access to tag memory still > dispatches. Only as MAIR_EL1 remains MAIR_ATTR_NORMAL, instead of > MAIR_ATTR_NORMAL_TAGGED, the access will stop. > > From the manual, I think ATA only affects TAG instructions like STG, > IRG, but not the tag access within normal STR/LDR. The ARM ARM states SCTLR_EL1.ATA0 == 0 means "access to allocation tags is prevented". The AArch64.MemSingle[] pseudocode ends up with similar checks: https://developer.arm.com/documentation/ddi0596/2021-09/Shared-Pseudocode/AArch64-Functions?lang=en#AArch64.MemSingle.read.5 before reading the tags from memory in AArch64.CheckTag(): https://developer.arm.com/documentation/ddi0596/2021-09/Shared-Pseudocode/AArch64-Functions?lang=en#AArch64.CheckTag.4 My suggestion is to raise this with support@arm.com (feel free to cc me) so that we clarify the hardware behaviour. I don't think it's entirely correct (it's more like, is there a risk of external aborts caused by access to allocation tag storage that's not present?) -- Catalin _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81FA0C433F5 for ; Tue, 14 Dec 2021 12:12:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TwmXmmg8DEAoPMltS/vH0hNJ1iUo6zMDZKz3eOgNaNw=; b=WquTSpsz6bWqlq 3DmpYCviCzByBuA5nK43tHuiav30qgmGLWpEE6JIQKwIG41L2Ez9cnzBcRZ9Qx+rtC4oVZViHGf4b kVFfYpUlFaPdIQMWvvDlqe7FowLh8US1pFTaLQaiZ3EqZxlVoDkiWD68wzJp/97DiLoTxxqLB0fja D70K6hPmBCW6OR7dtPE+aaTPlIBmoLlcnkVZN1Quasm7+8E2S15RXTQSgdYZAcmijOyCvxISQI/+O F93UydDKVYuxBhby3BnZnLfL/Zxx3tKj9syGsj+HBbV5wonle1AY/j3dGaFp5SeRmUh9NqdtGjida DfkEA5HzAfUDvMTflgVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx6dp-00DqzZ-SO; Tue, 14 Dec 2021 12:10:46 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mx6Vw-00DozJ-7L; Tue, 14 Dec 2021 12:02:37 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 97ABE614A2; Tue, 14 Dec 2021 12:02:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CAB6C34601; Tue, 14 Dec 2021 12:02:30 +0000 (UTC) Date: Tue, 14 Dec 2021 12:02:27 +0000 From: Catalin Marinas To: Yee Lee Cc: linux-kernel@vger.kernel.org, nicholas.Tang@mediatek.com, Kuan-Ying.lee@mediatek.com, chinwen.chang@mediatek.com, Jonathan Corbet , Will Deacon , Matthias Brugger , "Paul E. McKenney" , Randy Dunlap , Andrew Morton , Thomas Gleixner , "Maciej W. Rozycki" , Viresh Kumar , Peter Zijlstra , Vlastimil Babka , Marc Zyngier , David Brazdil , Ard Biesheuvel , Fuad Tabba , "open list:DOCUMENTATION" , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , "moderated list:ARM/Mediatek SoC support" Subject: Re: [PATCH v3 1/1] arm64/cpufeature: Optionally disable MTE via command-line Message-ID: References: <20210730144957.30938-1-yee.lee@mediatek.com> <20210730144957.30938-2-yee.lee@mediatek.com> <20210802153036.GH18685@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211214_040236_399193_726AED40 X-CRM114-Status: GOOD ( 25.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 14, 2021 at 04:19:05PM +0800, Yee Lee wrote: > On Fri, 2021-12-03 at 16:33 +0000, Catalin Marinas wrote: > > On Thu, Nov 25, 2021 at 06:19:29PM +0800, Yee Lee wrote: > > > As pointed out earlier, the hardware has been verified that still has > > > transaction sending to DRAM due to mair_el1(Normal_tagged) is > > > setup. That means the override in this patch would be incompleted and > > > cannot achieve to avoid undesired hardware confliction by disabling MTE. > > > > > > Do we have other options to delay the configuration on MAIR_EL1 after > > > the override? Or maybe another CONFIG to bypass the init in __cpu_setup? > > > > This register is trickier as it may be cached in the TLB (IIRC). I think > > deferring the setting of SCTLR_EL1.ATA(0) should be sufficient. Can you > > try the diff I sent in the previous email and confirm that the accesses > > to the allocation tag storage are blocked? > > Yes, the previous diff is already online. > > In our experiment, with cmdline, "arm64.nomte", cpu_enable_mte() is > bypassed and the ATA0 is not set, but the access to tag memory still > dispatches. Only as MAIR_EL1 remains MAIR_ATTR_NORMAL, instead of > MAIR_ATTR_NORMAL_TAGGED, the access will stop. > > From the manual, I think ATA only affects TAG instructions like STG, > IRG, but not the tag access within normal STR/LDR. The ARM ARM states SCTLR_EL1.ATA0 == 0 means "access to allocation tags is prevented". The AArch64.MemSingle[] pseudocode ends up with similar checks: https://developer.arm.com/documentation/ddi0596/2021-09/Shared-Pseudocode/AArch64-Functions?lang=en#AArch64.MemSingle.read.5 before reading the tags from memory in AArch64.CheckTag(): https://developer.arm.com/documentation/ddi0596/2021-09/Shared-Pseudocode/AArch64-Functions?lang=en#AArch64.CheckTag.4 My suggestion is to raise this with support@arm.com (feel free to cc me) so that we clarify the hardware behaviour. I don't think it's entirely correct (it's more like, is there a risk of external aborts caused by access to allocation tag storage that's not present?) -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel