From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8670C433FE for ; Tue, 14 Dec 2021 19:25:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234365AbhLNTZH (ORCPT ); Tue, 14 Dec 2021 14:25:07 -0500 Received: from mail-ot1-f47.google.com ([209.85.210.47]:35538 "EHLO mail-ot1-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234275AbhLNTZG (ORCPT ); Tue, 14 Dec 2021 14:25:06 -0500 Received: by mail-ot1-f47.google.com with SMTP id x43-20020a056830246b00b00570d09d34ebso22076330otr.2; Tue, 14 Dec 2021 11:25:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=ehX+3DJbXBjGHccd4UxxHLFi5H4zFHeokElr31tDsV4=; b=l+//42hn03lwwpD2eNeSaqPltZffOXu4zgtr1hLveVdRZ4Dk6f62fk/j6q7nPHIgpy unl0ni3TifHSvQBv7bwon+bFwitwt5qwrKQyuH77KMGl7f+nZMRjxzAa79ALDDExNrRd alxWTJLmFFC4N2Roz7cpbkp011yqRYIvZ3IpOIy6mjOJxNsJ74Ao7Wr2V0ZxO271K1V3 IGnEkERA3s+YnPY51X3jvo4n+RGsfZIUSbhDjUcCs6tuQ3IKZ6i51QCvBQWoF4/+Rk7G px1Rl9dZ0xDW1YblW9l5TMSav5UG0EqjOEfDqm6/ZgXykVYIYP1YLASuaRH4Bq0EyjI2 InjA== X-Gm-Message-State: AOAM533WKi7/45DB873qQsxevjEbsi8L+eVsZuLUt3hLtQoJwZlNIs0r rALIKoQOSgnxAEkT/Bt5hQ== X-Google-Smtp-Source: ABdhPJwu1jtseHaGInt4Zd2I+MrBQntRx58iFI0349+rwEjHZmbf1ZznDQ8wYliHroSvnVQAj6PUHQ== X-Received: by 2002:a9d:a16:: with SMTP id 22mr5901834otg.57.1639509906121; Tue, 14 Dec 2021 11:25:06 -0800 (PST) Received: from robh.at.kernel.org (66-90-148-213.dyn.grandenetworks.net. [66.90.148.213]) by smtp.gmail.com with ESMTPSA id y17sm141839ote.48.2021.12.14.11.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 11:25:05 -0800 (PST) Received: (nullmailer pid 3763381 invoked by uid 1000); Tue, 14 Dec 2021 19:25:04 -0000 Date: Tue, 14 Dec 2021 13:25:04 -0600 From: Rob Herring To: Biju Das Cc: Robin Murphy , dri-devel@lists.freedesktop.org, Daniel Vetter , tomeu.vizoso@collabora.com, Geert Uytterhoeven , Prabhakar Mahadev Lad , Alyssa Rosenzweig , devicetree@vger.kernel.org, David Airlie , Chris Paterson , linux-renesas-soc@vger.kernel.org, Rob Herring , Biju Das , Steven Price Subject: Re: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support Message-ID: References: <20211208104026.421-1-biju.das.jz@bp.renesas.com> <20211208104026.421-2-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211208104026.421-2-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, 08 Dec 2021 10:40:24 +0000, Biju Das wrote: > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, > add a compatible string for it. > > Signed-off-by: Biju Das > Reviewed-by: Lad Prabhakar > --- > v2->v3: > * Moved optional clock-names and reset-names to SoC-specific conditional schemas. > * minimum number of reset for the generic GPU is set to 1. > * Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L > SoC-specific conditional schemas. > v1->v2: > * Updated minItems for resets as 2 > * Documented optional property reset-names > * Documented reset-names as required property for RZ/G2L SoC. > --- > .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- > 1 file changed, 43 insertions(+), 2 deletions(-) > Applied, thanks! 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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id y17sm141839ote.48.2021.12.14.11.25.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Dec 2021 11:25:05 -0800 (PST) Received: (nullmailer pid 3763381 invoked by uid 1000); Tue, 14 Dec 2021 19:25:04 -0000 Date: Tue, 14 Dec 2021 13:25:04 -0600 From: Rob Herring To: Biju Das Subject: Re: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support Message-ID: References: <20211208104026.421-1-biju.das.jz@bp.renesas.com> <20211208104026.421-2-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211208104026.421-2-biju.das.jz@bp.renesas.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Chris Paterson , Geert Uytterhoeven , tomeu.vizoso@collabora.com, David Airlie , Prabhakar Mahadev Lad , dri-devel@lists.freedesktop.org, Biju Das , linux-renesas-soc@vger.kernel.org, Rob Herring , Alyssa Rosenzweig , Steven Price , Robin Murphy Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, 08 Dec 2021 10:40:24 +0000, Biju Das wrote: > The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, > add a compatible string for it. > > Signed-off-by: Biju Das > Reviewed-by: Lad Prabhakar > --- > v2->v3: > * Moved optional clock-names and reset-names to SoC-specific conditional schemas. > * minimum number of reset for the generic GPU is set to 1. > * Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L > SoC-specific conditional schemas. > v1->v2: > * Updated minItems for resets as 2 > * Documented optional property reset-names > * Documented reset-names as required property for RZ/G2L SoC. > --- > .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- > 1 file changed, 43 insertions(+), 2 deletions(-) > Applied, thanks!