From: Rob Herring <robh@kernel.org> To: Sascha Hauer <s.hauer@pengutronix.de> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, "Andy Yan" <andy.yan@rock-chips.com>, "Benjamin Gaignard" <benjamin.gaignard@collabora.com>, "Michael Riesch" <michael.riesch@wolfvision.net>, "Sandy Huang" <hjc@rock-chips.com>, "Heiko Stübner" <heiko@sntech.de>, "Peter Geis" <pgwipeout@gmail.com> Subject: Re: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Date: Tue, 21 Dec 2021 10:33:51 -0400 [thread overview] Message-ID: <YcHlzzuvxMGpPaRa@robh.at.kernel.org> (raw) In-Reply-To: <20211220110630.3521121-12-s.hauer@pengutronix.de> On Mon, Dec 20, 2021 at 12:06:19PM +0100, Sascha Hauer wrote: > The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. > The binding differs slightly from the existing VOP binding, so add a new > binding file for it. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > new file mode 100644 > index 0000000000000..df14d5aa85c85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoC display controller (VOP2) > + > +description: > + VOP2 (Video Output Processor v2) is the display controller for the Rockchip > + series of SoCs which transfers the image data from a video memory > + buffer to an external LCD interface. > + > +maintainers: > + - Sandy Huang <hjc@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3566-vop > + - rockchip,rk3568-vop > + > + reg: > + minItems: 1 > + items: > + - description: > + Must contain one entry corresponding to the base address and length > + of the register space. > + - description: > + Can optionally contain a second entry corresponding to > + the CRTC gamma LUT address. > + > + interrupts: > + maxItems: 1 > + description: > + The VOP interrupt is shared by several interrupt sources, such as > + frame start (VSYNC), line flag and other status interrupts. > + > + clocks: > + items: > + - description: Clock for ddr buffer transfer. > + - description: Clock for the ahb bus to R/W the phy regs. > + - description: Pixel clock for video port 0. > + - description: Pixel clock for video port 1. > + - description: Pixel clock for video port 2. > + > + clock-names: > + items: > + - const: aclk_vop > + - const: hclk_vop _vop is redundant. > + - const: dclk_vp0 > + - const: dclk_vp1 > + - const: dclk_vp2 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to GRF regs used for misc control > + > + ports: > + $ref: /schemas/graph.yaml#/properties/port s/port/ports/ > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP0 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP1 > + > + port@: port@2 > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP2 > + > + assigned-clocks: true > + > + assigned-clock-rates: true > + > + assigned-clock-parents: true These are automatically added. > + > + iommus: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3568-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/rk3568-power.h> > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + vop: vop@fe040000 { > + compatible = "rockchip,rk3568-vop"; > + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru ACLK_VOP>, > + <&cru HCLK_VOP>, > + <&cru DCLK_VOP0>, > + <&cru DCLK_VOP1>, > + <&cru DCLK_VOP2>; > + clock-names = "aclk_vop", > + "hclk_vop", > + "dclk_vp0", > + "dclk_vp1", > + "dclk_vp2"; > + power-domains = <&power RK3568_PD_VO>; > + iommus = <&vop_mmu>; > + vop_out: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + vp0: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp1: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp2: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + }; > -- > 2.30.2 > >
WARNING: multiple messages have this Message-ID
From: Rob Herring <robh@kernel.org> To: Sascha Hauer <s.hauer@pengutronix.de> Cc: devicetree@vger.kernel.org, Benjamin Gaignard <benjamin.gaignard@collabora.com>, Peter Geis <pgwipeout@gmail.com>, Sandy Huang <hjc@rock-chips.com>, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Michael Riesch <michael.riesch@wolfvision.net>, kernel@pengutronix.de, Andy Yan <andy.yan@rock-chips.com>, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Date: Tue, 21 Dec 2021 10:33:51 -0400 [thread overview] Message-ID: <YcHlzzuvxMGpPaRa@robh.at.kernel.org> (raw) In-Reply-To: <20211220110630.3521121-12-s.hauer@pengutronix.de> On Mon, Dec 20, 2021 at 12:06:19PM +0100, Sascha Hauer wrote: > The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. > The binding differs slightly from the existing VOP binding, so add a new > binding file for it. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > new file mode 100644 > index 0000000000000..df14d5aa85c85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoC display controller (VOP2) > + > +description: > + VOP2 (Video Output Processor v2) is the display controller for the Rockchip > + series of SoCs which transfers the image data from a video memory > + buffer to an external LCD interface. > + > +maintainers: > + - Sandy Huang <hjc@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3566-vop > + - rockchip,rk3568-vop > + > + reg: > + minItems: 1 > + items: > + - description: > + Must contain one entry corresponding to the base address and length > + of the register space. > + - description: > + Can optionally contain a second entry corresponding to > + the CRTC gamma LUT address. > + > + interrupts: > + maxItems: 1 > + description: > + The VOP interrupt is shared by several interrupt sources, such as > + frame start (VSYNC), line flag and other status interrupts. > + > + clocks: > + items: > + - description: Clock for ddr buffer transfer. > + - description: Clock for the ahb bus to R/W the phy regs. > + - description: Pixel clock for video port 0. > + - description: Pixel clock for video port 1. > + - description: Pixel clock for video port 2. > + > + clock-names: > + items: > + - const: aclk_vop > + - const: hclk_vop _vop is redundant. > + - const: dclk_vp0 > + - const: dclk_vp1 > + - const: dclk_vp2 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to GRF regs used for misc control > + > + ports: > + $ref: /schemas/graph.yaml#/properties/port s/port/ports/ > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP0 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP1 > + > + port@: port@2 > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP2 > + > + assigned-clocks: true > + > + assigned-clock-rates: true > + > + assigned-clock-parents: true These are automatically added. > + > + iommus: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3568-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/rk3568-power.h> > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + vop: vop@fe040000 { > + compatible = "rockchip,rk3568-vop"; > + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru ACLK_VOP>, > + <&cru HCLK_VOP>, > + <&cru DCLK_VOP0>, > + <&cru DCLK_VOP1>, > + <&cru DCLK_VOP2>; > + clock-names = "aclk_vop", > + "hclk_vop", > + "dclk_vp0", > + "dclk_vp1", > + "dclk_vp2"; > + power-domains = <&power RK3568_PD_VO>; > + iommus = <&vop_mmu>; > + vop_out: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + vp0: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp1: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp2: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + }; > -- > 2.30.2 > >
WARNING: multiple messages have this Message-ID
From: Rob Herring <robh@kernel.org> To: Sascha Hauer <s.hauer@pengutronix.de> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, "Andy Yan" <andy.yan@rock-chips.com>, "Benjamin Gaignard" <benjamin.gaignard@collabora.com>, "Michael Riesch" <michael.riesch@wolfvision.net>, "Sandy Huang" <hjc@rock-chips.com>, "Heiko Stübner" <heiko@sntech.de>, "Peter Geis" <pgwipeout@gmail.com> Subject: Re: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Date: Tue, 21 Dec 2021 10:33:51 -0400 [thread overview] Message-ID: <YcHlzzuvxMGpPaRa@robh.at.kernel.org> (raw) In-Reply-To: <20211220110630.3521121-12-s.hauer@pengutronix.de> On Mon, Dec 20, 2021 at 12:06:19PM +0100, Sascha Hauer wrote: > The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. > The binding differs slightly from the existing VOP binding, so add a new > binding file for it. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > new file mode 100644 > index 0000000000000..df14d5aa85c85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoC display controller (VOP2) > + > +description: > + VOP2 (Video Output Processor v2) is the display controller for the Rockchip > + series of SoCs which transfers the image data from a video memory > + buffer to an external LCD interface. > + > +maintainers: > + - Sandy Huang <hjc@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3566-vop > + - rockchip,rk3568-vop > + > + reg: > + minItems: 1 > + items: > + - description: > + Must contain one entry corresponding to the base address and length > + of the register space. > + - description: > + Can optionally contain a second entry corresponding to > + the CRTC gamma LUT address. > + > + interrupts: > + maxItems: 1 > + description: > + The VOP interrupt is shared by several interrupt sources, such as > + frame start (VSYNC), line flag and other status interrupts. > + > + clocks: > + items: > + - description: Clock for ddr buffer transfer. > + - description: Clock for the ahb bus to R/W the phy regs. > + - description: Pixel clock for video port 0. > + - description: Pixel clock for video port 1. > + - description: Pixel clock for video port 2. > + > + clock-names: > + items: > + - const: aclk_vop > + - const: hclk_vop _vop is redundant. > + - const: dclk_vp0 > + - const: dclk_vp1 > + - const: dclk_vp2 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to GRF regs used for misc control > + > + ports: > + $ref: /schemas/graph.yaml#/properties/port s/port/ports/ > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP0 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP1 > + > + port@: port@2 > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP2 > + > + assigned-clocks: true > + > + assigned-clock-rates: true > + > + assigned-clock-parents: true These are automatically added. > + > + iommus: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3568-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/rk3568-power.h> > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + vop: vop@fe040000 { > + compatible = "rockchip,rk3568-vop"; > + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru ACLK_VOP>, > + <&cru HCLK_VOP>, > + <&cru DCLK_VOP0>, > + <&cru DCLK_VOP1>, > + <&cru DCLK_VOP2>; > + clock-names = "aclk_vop", > + "hclk_vop", > + "dclk_vp0", > + "dclk_vp1", > + "dclk_vp2"; > + power-domains = <&power RK3568_PD_VO>; > + iommus = <&vop_mmu>; > + vop_out: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + vp0: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp1: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp2: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + }; > -- > 2.30.2 > > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID
From: Rob Herring <robh@kernel.org> To: Sascha Hauer <s.hauer@pengutronix.de> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, "Andy Yan" <andy.yan@rock-chips.com>, "Benjamin Gaignard" <benjamin.gaignard@collabora.com>, "Michael Riesch" <michael.riesch@wolfvision.net>, "Sandy Huang" <hjc@rock-chips.com>, "Heiko Stübner" <heiko@sntech.de>, "Peter Geis" <pgwipeout@gmail.com> Subject: Re: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Date: Tue, 21 Dec 2021 10:33:51 -0400 [thread overview] Message-ID: <YcHlzzuvxMGpPaRa@robh.at.kernel.org> (raw) In-Reply-To: <20211220110630.3521121-12-s.hauer@pengutronix.de> On Mon, Dec 20, 2021 at 12:06:19PM +0100, Sascha Hauer wrote: > The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566. > The binding differs slightly from the existing VOP binding, so add a new > binding file for it. > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > .../display/rockchip/rockchip-vop2.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > > diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > new file mode 100644 > index 0000000000000..df14d5aa85c85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip SoC display controller (VOP2) > + > +description: > + VOP2 (Video Output Processor v2) is the display controller for the Rockchip > + series of SoCs which transfers the image data from a video memory > + buffer to an external LCD interface. > + > +maintainers: > + - Sandy Huang <hjc@rock-chips.com> > + - Heiko Stuebner <heiko@sntech.de> > + > +properties: > + compatible: > + enum: > + - rockchip,rk3566-vop > + - rockchip,rk3568-vop > + > + reg: > + minItems: 1 > + items: > + - description: > + Must contain one entry corresponding to the base address and length > + of the register space. > + - description: > + Can optionally contain a second entry corresponding to > + the CRTC gamma LUT address. > + > + interrupts: > + maxItems: 1 > + description: > + The VOP interrupt is shared by several interrupt sources, such as > + frame start (VSYNC), line flag and other status interrupts. > + > + clocks: > + items: > + - description: Clock for ddr buffer transfer. > + - description: Clock for the ahb bus to R/W the phy regs. > + - description: Pixel clock for video port 0. > + - description: Pixel clock for video port 1. > + - description: Pixel clock for video port 2. > + > + clock-names: > + items: > + - const: aclk_vop > + - const: hclk_vop _vop is redundant. > + - const: dclk_vp0 > + - const: dclk_vp1 > + - const: dclk_vp2 > + > + rockchip,grf: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + Phandle to GRF regs used for misc control > + > + ports: > + $ref: /schemas/graph.yaml#/properties/port s/port/ports/ > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP0 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP1 > + > + port@: port@2 > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of VP2 > + > + assigned-clocks: true > + > + assigned-clock-rates: true > + > + assigned-clock-parents: true These are automatically added. > + > + iommus: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3568-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/rk3568-power.h> > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + vop: vop@fe040000 { > + compatible = "rockchip,rk3568-vop"; > + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru ACLK_VOP>, > + <&cru HCLK_VOP>, > + <&cru DCLK_VOP0>, > + <&cru DCLK_VOP1>, > + <&cru DCLK_VOP2>; > + clock-names = "aclk_vop", > + "hclk_vop", > + "dclk_vp0", > + "dclk_vp1", > + "dclk_vp2"; > + power-domains = <&power RK3568_PD_VO>; > + iommus = <&vop_mmu>; > + vop_out: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + vp0: port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp1: port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + vp2: port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + }; > -- > 2.30.2 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-12-21 14:33 UTC|newest] Thread overview: 189+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 01/22] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 02/22] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 03/22] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 04/22] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 05/22] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 06/22] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 07/22] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 11:06 ` [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-21 14:31 ` Rob Herring 2021-12-21 14:31 ` Rob Herring 2021-12-21 14:31 ` Rob Herring 2021-12-21 14:31 ` Rob Herring 2021-12-22 10:47 ` Sascha Hauer 2021-12-22 10:47 ` Sascha Hauer 2021-12-22 10:47 ` Sascha Hauer 2021-12-22 10:47 ` Sascha Hauer 2021-12-22 13:52 ` Rob Herring 2021-12-22 13:52 ` Rob Herring 2021-12-22 13:52 ` Rob Herring 2021-12-22 13:52 ` Rob Herring 2021-12-22 19:39 ` Heiko Stübner 2021-12-22 19:39 ` Heiko Stübner 2021-12-22 19:39 ` Heiko Stübner 2021-12-22 19:39 ` Heiko Stübner 2021-12-22 19:44 ` Nicolas Frattaroli 2021-12-22 19:44 ` Nicolas Frattaroli 2021-12-22 19:44 ` Nicolas Frattaroli 2021-12-22 19:44 ` Nicolas Frattaroli 2021-12-22 19:56 ` Rob Herring 2021-12-22 19:56 ` Rob Herring 2021-12-22 19:56 ` Rob Herring 2021-12-22 19:56 ` Rob Herring 2021-12-20 11:06 ` [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator support Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 11:06 ` [PATCH 10/22] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-20 14:27 ` Rob Herring 2021-12-21 14:33 ` Rob Herring [this message] 2021-12-21 14:33 ` Rob Herring 2021-12-21 14:33 ` Rob Herring 2021-12-21 14:33 ` Rob Herring 2021-12-20 11:06 ` [PATCH 12/22] arm64: dts: rockchip: rk3399: reorder hmdi clocks Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 13/22] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 14/22] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 15/22] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 16/22] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 17/22] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 18/22] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop* Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 19/22] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-21 17:31 ` Heiko Stübner 2021-12-21 17:31 ` Heiko Stübner 2021-12-21 17:31 ` Heiko Stübner 2021-12-21 17:31 ` Heiko Stübner 2021-12-20 11:06 ` [PATCH 21/22] drm/rockchip: Make VOP driver optional Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` [PATCH 22/22] drm: rockchip: Add VOP2 driver Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 11:06 ` Sascha Hauer 2021-12-20 14:16 ` Nicolas Frattaroli 2021-12-20 14:16 ` Nicolas Frattaroli 2021-12-20 14:16 ` Nicolas Frattaroli 2021-12-20 14:16 ` Nicolas Frattaroli 2021-12-20 16:53 ` Nicolas Frattaroli 2021-12-20 16:53 ` Nicolas Frattaroli 2021-12-20 16:53 ` Nicolas Frattaroli 2021-12-20 16:53 ` Nicolas Frattaroli 2021-12-20 18:51 ` Sascha Hauer 2021-12-20 18:51 ` Sascha Hauer 2021-12-20 18:51 ` Sascha Hauer 2021-12-20 18:51 ` Sascha Hauer 2021-12-20 23:20 ` kernel test robot 2021-12-20 23:20 ` kernel test robot 2021-12-20 23:20 ` kernel test robot 2021-12-21 13:44 ` Nicolas Frattaroli 2021-12-21 13:44 ` Nicolas Frattaroli 2021-12-21 13:44 ` Nicolas Frattaroli 2021-12-21 13:44 ` Nicolas Frattaroli 2021-12-22 17:07 ` Nicolas Frattaroli 2021-12-22 17:07 ` Nicolas Frattaroli 2021-12-22 17:07 ` Nicolas Frattaroli 2021-12-22 17:07 ` Nicolas Frattaroli 2022-01-03 14:55 ` Sascha Hauer 2022-01-03 14:55 ` Sascha Hauer 2022-01-03 14:55 ` Sascha Hauer 2022-01-03 14:55 ` Sascha Hauer 2022-01-04 11:07 ` Andy Yan 2022-01-04 11:07 ` Andy Yan 2022-01-04 11:07 ` Andy Yan 2022-01-05 12:20 ` Sascha Hauer 2022-01-05 12:20 ` Sascha Hauer 2022-01-05 12:20 ` Sascha Hauer 2022-01-05 12:20 ` Sascha Hauer 2021-12-20 11:51 ` [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Nicolas Frattaroli 2021-12-20 11:51 ` Nicolas Frattaroli 2021-12-20 11:51 ` Nicolas Frattaroli 2021-12-20 11:51 ` Nicolas Frattaroli 2022-01-19 11:29 ` Piotr Oniszczuk 2022-01-19 11:29 ` Piotr Oniszczuk 2022-01-19 11:29 ` Piotr Oniszczuk 2022-01-19 11:29 ` Piotr Oniszczuk 2022-01-21 10:32 ` Sascha Hauer 2022-01-21 10:32 ` Sascha Hauer 2022-01-21 10:32 ` Sascha Hauer 2022-01-21 10:32 ` Sascha Hauer 2022-01-21 15:43 ` Piotr Oniszczuk 2022-01-21 15:43 ` Piotr Oniszczuk 2022-01-21 15:43 ` Piotr Oniszczuk 2022-01-21 15:43 ` Piotr Oniszczuk
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=YcHlzzuvxMGpPaRa@robh.at.kernel.org \ --to=robh@kernel.org \ --cc=andy.yan@rock-chips.com \ --cc=benjamin.gaignard@collabora.com \ --cc=devicetree@vger.kernel.org \ --cc=dri-devel@lists.freedesktop.org \ --cc=heiko@sntech.de \ --cc=hjc@rock-chips.com \ --cc=kernel@pengutronix.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-rockchip@lists.infradead.org \ --cc=michael.riesch@wolfvision.net \ --cc=pgwipeout@gmail.com \ --cc=s.hauer@pengutronix.de \ --subject='Re: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.