* [PATCH 1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Exynos7 devicetree bindings require more input clocks for TOP0 and
PERIC1 clock controllers, than already provided. Existing DTS was not
matching the bindings, so let's update the DTS, even though the error
could be in the bindings.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 33 ++++++++++++++++++++-----
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index c3efbc8add38..3e53ff2be455 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -177,10 +177,11 @@ clock_top0: clock-controller@105d0000 {
clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
<&clock_topc DOUT_SCLK_BUS1_PLL>,
<&clock_topc DOUT_SCLK_CC_PLL>,
- <&clock_topc DOUT_SCLK_MFC_PLL>;
+ <&clock_topc DOUT_SCLK_MFC_PLL>,
+ <&clock_topc DOUT_SCLK_AUD_PLL>;
clock-names = "fin_pll", "dout_sclk_bus0_pll",
"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
- "dout_sclk_mfc_pll";
+ "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
};
clock_top1: clock-controller@105e0000 {
@@ -218,12 +219,32 @@ clock_peric1: clock-controller@14c80000 {
compatible = "samsung,exynos7-clock-peric1";
reg = <0x14c80000 0xd00>;
#clock-cells = <1>;
- clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+ clocks = <&fin_pll>,
+ <&clock_top0 DOUT_ACLK_PERIC1>,
<&clock_top0 CLK_SCLK_UART1>,
<&clock_top0 CLK_SCLK_UART2>,
- <&clock_top0 CLK_SCLK_UART3>;
- clock-names = "fin_pll", "dout_aclk_peric1_66",
- "sclk_uart1", "sclk_uart2", "sclk_uart3";
+ <&clock_top0 CLK_SCLK_UART3>,
+ <&clock_top0 CLK_SCLK_SPI0>,
+ <&clock_top0 CLK_SCLK_SPI1>,
+ <&clock_top0 CLK_SCLK_SPI2>,
+ <&clock_top0 CLK_SCLK_SPI3>,
+ <&clock_top0 CLK_SCLK_SPI4>,
+ <&clock_top0 CLK_SCLK_I2S1>,
+ <&clock_top0 CLK_SCLK_PCM1>,
+ <&clock_top0 CLK_SCLK_SPDIF>;
+ clock-names = "fin_pll",
+ "dout_aclk_peric1_66",
+ "sclk_uart1",
+ "sclk_uart2",
+ "sclk_uart3",
+ "sclk_spi0",
+ "sclk_spi1",
+ "sclk_spi2",
+ "sclk_spi3",
+ "sclk_spi4",
+ "sclk_i2s1",
+ "sclk_pcm1",
+ "sclk_spdif";
};
clock_peris: clock-controller@10040000 {
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Exynos7 devicetree bindings require more input clocks for TOP0 and
PERIC1 clock controllers, than already provided. Existing DTS was not
matching the bindings, so let's update the DTS, even though the error
could be in the bindings.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm64/boot/dts/exynos/exynos7.dtsi | 33 ++++++++++++++++++++-----
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index c3efbc8add38..3e53ff2be455 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -177,10 +177,11 @@ clock_top0: clock-controller@105d0000 {
clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
<&clock_topc DOUT_SCLK_BUS1_PLL>,
<&clock_topc DOUT_SCLK_CC_PLL>,
- <&clock_topc DOUT_SCLK_MFC_PLL>;
+ <&clock_topc DOUT_SCLK_MFC_PLL>,
+ <&clock_topc DOUT_SCLK_AUD_PLL>;
clock-names = "fin_pll", "dout_sclk_bus0_pll",
"dout_sclk_bus1_pll", "dout_sclk_cc_pll",
- "dout_sclk_mfc_pll";
+ "dout_sclk_mfc_pll", "dout_sclk_aud_pll";
};
clock_top1: clock-controller@105e0000 {
@@ -218,12 +219,32 @@ clock_peric1: clock-controller@14c80000 {
compatible = "samsung,exynos7-clock-peric1";
reg = <0x14c80000 0xd00>;
#clock-cells = <1>;
- clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+ clocks = <&fin_pll>,
+ <&clock_top0 DOUT_ACLK_PERIC1>,
<&clock_top0 CLK_SCLK_UART1>,
<&clock_top0 CLK_SCLK_UART2>,
- <&clock_top0 CLK_SCLK_UART3>;
- clock-names = "fin_pll", "dout_aclk_peric1_66",
- "sclk_uart1", "sclk_uart2", "sclk_uart3";
+ <&clock_top0 CLK_SCLK_UART3>,
+ <&clock_top0 CLK_SCLK_SPI0>,
+ <&clock_top0 CLK_SCLK_SPI1>,
+ <&clock_top0 CLK_SCLK_SPI2>,
+ <&clock_top0 CLK_SCLK_SPI3>,
+ <&clock_top0 CLK_SCLK_SPI4>,
+ <&clock_top0 CLK_SCLK_I2S1>,
+ <&clock_top0 CLK_SCLK_PCM1>,
+ <&clock_top0 CLK_SCLK_SPDIF>;
+ clock-names = "fin_pll",
+ "dout_aclk_peric1_66",
+ "sclk_uart1",
+ "sclk_uart2",
+ "sclk_uart3",
+ "sclk_spi0",
+ "sclk_spi1",
+ "sclk_spi2",
+ "sclk_spi3",
+ "sclk_spi4",
+ "sclk_i2s1",
+ "sclk_pcm1",
+ "sclk_spdif";
};
clock_peris: clock-controller@10040000 {
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 2/8] ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Exynos5260 bindings require to feed clock controllers with certain clock
inputs. The IO clocks are expected to be provided by the board. The
PHY clocks are usually followed by mux which can choose between the PHY
clock and main 24 MHz oscillator, so skip defining them and just use the
latter one.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5260-xyref5260.dts | 21 ++++
arch/arm/boot/dts/exynos5260.dtsi | 128 +++++++++++++++++++++
2 files changed, 149 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 0dc2ec16aa0a..c404fdb0fe19 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -29,6 +29,27 @@ fin_pll: xxti {
#clock-cells = <0>;
};
+ ioclk_pcm: clock-pcm-ext {
+ compatible = "fixed-clock";
+ clock-frequency = <2048000>;
+ clock-output-names = "ioclk_pcm_extclk";
+ #clock-cells = <0>;
+ };
+
+ ioclk_i2s: clock-i2s-cd {
+ compatible = "fixed-clock";
+ clock-frequency = <147456000>;
+ clock-output-names = "ioclk_i2s_cdclk";
+ #clock-cells = <0>;
+ };
+
+ ioclk_spdif: clock-spdif-ext {
+ compatible = "fixed-clock";
+ clock-frequency = <49152000>;
+ clock-output-names = "ioclk_spdif_extclk";
+ #clock-cells = <0>;
+ };
+
xrtcxti: xrtcxti {
compatible = "fixed-clock";
clock-frequency = <32768>;
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 524d244050e0..56271e7c4587 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -113,78 +113,206 @@ clock_top: clock-controller@10010000 {
compatible = "samsung,exynos5260-clock-top";
reg = <0x10010000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEM_PLL>,
+ <&clock_mif MIF_DOUT_BUS_PLL>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_mem_pll",
+ "dout_bus_pll",
+ "dout_media_pll";
};
clock_peri: clock-controller@10200000 {
compatible = "samsung,exynos5260-clock-peri";
reg = <0x10200000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&ioclk_pcm>,
+ <&ioclk_i2s>,
+ <&ioclk_spdif>,
+ <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_PERI_66>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART0>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART1>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART2>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>,
+ <&clock_top TOP_DOUT_ACLK_PERI_AUD>;
+ clock-names = "fin_pll",
+ "ioclk_pcm_extclk",
+ "ioclk_i2s_cdclk",
+ "ioclk_spdif_extclk",
+ "phyclk_hdmi_phy_ref_cko",
+ "dout_aclk_peri_66",
+ "dout_sclk_peri_uart0",
+ "dout_sclk_peri_uart1",
+ "dout_sclk_peri_uart2",
+ "dout_sclk_peri_spi0_b",
+ "dout_sclk_peri_spi1_b",
+ "dout_sclk_peri_spi2_b",
+ "dout_aclk_peri_aud";
};
clock_egl: clock-controller@10600000 {
compatible = "samsung,exynos5260-clock-egl";
reg = <0x10600000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_BUS_PLL>;
+ clock-names = "fin_pll",
+ "dout_bus_pll";
};
clock_kfc: clock-controller@10700000 {
compatible = "samsung,exynos5260-clock-kfc";
reg = <0x10700000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_media_pll";
};
clock_g2d: clock-controller@10a00000 {
compatible = "samsung,exynos5260-clock-g2d";
reg = <0x10A00000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_G2D_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_g2d_333";
};
clock_mif: clock-controller@10ce0000 {
compatible = "samsung,exynos5260-clock-mif";
reg = <0x10CE0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
};
clock_mfc: clock-controller@11090000 {
compatible = "samsung,exynos5260-clock-mfc";
reg = <0x11090000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_MFC_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_mfc_333";
};
clock_g3d: clock-controller@11830000 {
compatible = "samsung,exynos5260-clock-g3d";
reg = <0x11830000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
};
clock_fsys: clock-controller@122e0000 {
compatible = "samsung,exynos5260-clock-fsys";
reg = <0x122E0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_FSYS_200>;
+ clock-names = "fin_pll",
+ "phyclk_usbhost20_phy_phyclock",
+ "phyclk_usbhost20_phy_freeclk",
+ "phyclk_usbhost20_phy_clk48mohci",
+ "phyclk_usbdrd30_udrd30_pipe_pclk",
+ "phyclk_usbdrd30_udrd30_phyclock",
+ "dout_aclk_fsys_200";
};
clock_aud: clock-controller@128c0000 {
compatible = "samsung,exynos5260-clock-aud";
reg = <0x128C0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_FOUT_AUD_PLL>,
+ <&ioclk_i2s>,
+ <&ioclk_pcm>;
+ clock-names = "fin_pll",
+ "fout_aud_pll",
+ "ioclk_i2s_cdclk",
+ "ioclk_pcm_extclk";
};
clock_isp: clock-controller@133c0000 {
compatible = "samsung,exynos5260-clock-isp";
reg = <0x133C0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_ISP1_266>,
+ <&clock_top TOP_DOUT_ACLK_ISP1_400>,
+ <&clock_top TOP_MOUT_ACLK_ISP1_266>;
+ clock-names = "fin_pll",
+ "dout_aclk_isp1_266",
+ "dout_aclk_isp1_400",
+ "mout_aclk_isp1_266";
};
clock_gscl: clock-controller@13f00000 {
compatible = "samsung,exynos5260-clock-gscl";
reg = <0x13F00000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_GSCL_400>,
+ <&clock_top TOP_DOUT_ACLK_GSCL_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_gscl_400",
+ "dout_aclk_gscl_333";
};
clock_disp: clock-controller@14550000 {
compatible = "samsung,exynos5260-clock-disp";
reg = <0x14550000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&ioclk_spdif>,
+ <&clock_top TOP_DOUT_ACLK_PERI_AUD>,
+ <&clock_top TOP_DOUT_ACLK_DISP_222>,
+ <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>,
+ <&clock_top TOP_DOUT_ACLK_DISP_333>;
+ clock-names = "fin_pll",
+ "phyclk_dptx_phy_ch3_txd_clk",
+ "phyclk_dptx_phy_ch2_txd_clk",
+ "phyclk_dptx_phy_ch1_txd_clk",
+ "phyclk_dptx_phy_ch0_txd_clk",
+ "phyclk_hdmi_phy_tmds_clko",
+ "phyclk_hdmi_phy_ref_clko",
+ "phyclk_hdmi_phy_pixel_clko",
+ "phyclk_hdmi_link_o_tmds_clkhi",
+ "phyclk_mipi_dphy_4l_m_txbyte_clkhs",
+ "phyclk_dptx_phy_o_ref_clk_24m",
+ "phyclk_dptx_phy_clk_div2",
+ "phyclk_mipi_dphy_4l_m_rxclkesc0",
+ "phyclk_hdmi_phy_ref_cko",
+ "ioclk_spdif_extclk",
+ "dout_aclk_peri_aud",
+ "dout_aclk_disp_222",
+ "dout_sclk_disp_pixel",
+ "dout_aclk_disp_333";
};
gic: interrupt-controller@10481000 {
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 2/8] ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Exynos5260 bindings require to feed clock controllers with certain clock
inputs. The IO clocks are expected to be provided by the board. The
PHY clocks are usually followed by mux which can choose between the PHY
clock and main 24 MHz oscillator, so skip defining them and just use the
latter one.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
arch/arm/boot/dts/exynos5260-xyref5260.dts | 21 ++++
arch/arm/boot/dts/exynos5260.dtsi | 128 +++++++++++++++++++++
2 files changed, 149 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
index 0dc2ec16aa0a..c404fdb0fe19 100644
--- a/arch/arm/boot/dts/exynos5260-xyref5260.dts
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -29,6 +29,27 @@ fin_pll: xxti {
#clock-cells = <0>;
};
+ ioclk_pcm: clock-pcm-ext {
+ compatible = "fixed-clock";
+ clock-frequency = <2048000>;
+ clock-output-names = "ioclk_pcm_extclk";
+ #clock-cells = <0>;
+ };
+
+ ioclk_i2s: clock-i2s-cd {
+ compatible = "fixed-clock";
+ clock-frequency = <147456000>;
+ clock-output-names = "ioclk_i2s_cdclk";
+ #clock-cells = <0>;
+ };
+
+ ioclk_spdif: clock-spdif-ext {
+ compatible = "fixed-clock";
+ clock-frequency = <49152000>;
+ clock-output-names = "ioclk_spdif_extclk";
+ #clock-cells = <0>;
+ };
+
xrtcxti: xrtcxti {
compatible = "fixed-clock";
clock-frequency = <32768>;
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 524d244050e0..56271e7c4587 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -113,78 +113,206 @@ clock_top: clock-controller@10010000 {
compatible = "samsung,exynos5260-clock-top";
reg = <0x10010000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEM_PLL>,
+ <&clock_mif MIF_DOUT_BUS_PLL>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_mem_pll",
+ "dout_bus_pll",
+ "dout_media_pll";
};
clock_peri: clock-controller@10200000 {
compatible = "samsung,exynos5260-clock-peri";
reg = <0x10200000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&ioclk_pcm>,
+ <&ioclk_i2s>,
+ <&ioclk_spdif>,
+ <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_PERI_66>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART0>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART1>,
+ <&clock_top TOP_DOUT_SCLK_PERI_UART2>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>,
+ <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>,
+ <&clock_top TOP_DOUT_ACLK_PERI_AUD>;
+ clock-names = "fin_pll",
+ "ioclk_pcm_extclk",
+ "ioclk_i2s_cdclk",
+ "ioclk_spdif_extclk",
+ "phyclk_hdmi_phy_ref_cko",
+ "dout_aclk_peri_66",
+ "dout_sclk_peri_uart0",
+ "dout_sclk_peri_uart1",
+ "dout_sclk_peri_uart2",
+ "dout_sclk_peri_spi0_b",
+ "dout_sclk_peri_spi1_b",
+ "dout_sclk_peri_spi2_b",
+ "dout_aclk_peri_aud";
};
clock_egl: clock-controller@10600000 {
compatible = "samsung,exynos5260-clock-egl";
reg = <0x10600000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_BUS_PLL>;
+ clock-names = "fin_pll",
+ "dout_bus_pll";
};
clock_kfc: clock-controller@10700000 {
compatible = "samsung,exynos5260-clock-kfc";
reg = <0x10700000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_media_pll";
};
clock_g2d: clock-controller@10a00000 {
compatible = "samsung,exynos5260-clock-g2d";
reg = <0x10A00000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_G2D_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_g2d_333";
};
clock_mif: clock-controller@10ce0000 {
compatible = "samsung,exynos5260-clock-mif";
reg = <0x10CE0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
};
clock_mfc: clock-controller@11090000 {
compatible = "samsung,exynos5260-clock-mfc";
reg = <0x11090000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_MFC_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_mfc_333";
};
clock_g3d: clock-controller@11830000 {
compatible = "samsung,exynos5260-clock-g3d";
reg = <0x11830000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
};
clock_fsys: clock-controller@122e0000 {
compatible = "samsung,exynos5260-clock-fsys";
reg = <0x122E0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_FSYS_200>;
+ clock-names = "fin_pll",
+ "phyclk_usbhost20_phy_phyclock",
+ "phyclk_usbhost20_phy_freeclk",
+ "phyclk_usbhost20_phy_clk48mohci",
+ "phyclk_usbdrd30_udrd30_pipe_pclk",
+ "phyclk_usbdrd30_udrd30_phyclock",
+ "dout_aclk_fsys_200";
};
clock_aud: clock-controller@128c0000 {
compatible = "samsung,exynos5260-clock-aud";
reg = <0x128C0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_FOUT_AUD_PLL>,
+ <&ioclk_i2s>,
+ <&ioclk_pcm>;
+ clock-names = "fin_pll",
+ "fout_aud_pll",
+ "ioclk_i2s_cdclk",
+ "ioclk_pcm_extclk";
};
clock_isp: clock-controller@133c0000 {
compatible = "samsung,exynos5260-clock-isp";
reg = <0x133C0000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_ISP1_266>,
+ <&clock_top TOP_DOUT_ACLK_ISP1_400>,
+ <&clock_top TOP_MOUT_ACLK_ISP1_266>;
+ clock-names = "fin_pll",
+ "dout_aclk_isp1_266",
+ "dout_aclk_isp1_400",
+ "mout_aclk_isp1_266";
};
clock_gscl: clock-controller@13f00000 {
compatible = "samsung,exynos5260-clock-gscl";
reg = <0x13F00000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_top TOP_DOUT_ACLK_GSCL_400>,
+ <&clock_top TOP_DOUT_ACLK_GSCL_333>;
+ clock-names = "fin_pll",
+ "dout_aclk_gscl_400",
+ "dout_aclk_gscl_333";
};
clock_disp: clock-controller@14550000 {
compatible = "samsung,exynos5260-clock-disp";
reg = <0x14550000 0x10000>;
#clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&fin_pll>,
+ <&ioclk_spdif>,
+ <&clock_top TOP_DOUT_ACLK_PERI_AUD>,
+ <&clock_top TOP_DOUT_ACLK_DISP_222>,
+ <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>,
+ <&clock_top TOP_DOUT_ACLK_DISP_333>;
+ clock-names = "fin_pll",
+ "phyclk_dptx_phy_ch3_txd_clk",
+ "phyclk_dptx_phy_ch2_txd_clk",
+ "phyclk_dptx_phy_ch1_txd_clk",
+ "phyclk_dptx_phy_ch0_txd_clk",
+ "phyclk_hdmi_phy_tmds_clko",
+ "phyclk_hdmi_phy_ref_clko",
+ "phyclk_hdmi_phy_pixel_clko",
+ "phyclk_hdmi_link_o_tmds_clkhi",
+ "phyclk_mipi_dphy_4l_m_txbyte_clkhs",
+ "phyclk_dptx_phy_o_ref_clk_24m",
+ "phyclk_dptx_phy_clk_div2",
+ "phyclk_mipi_dphy_4l_m_rxclkesc0",
+ "phyclk_hdmi_phy_ref_cko",
+ "ioclk_spdif_extclk",
+ "dout_aclk_peri_aud",
+ "dout_aclk_disp_222",
+ "dout_sclk_disp_pixel",
+ "dout_aclk_disp_333";
};
gic: interrupt-controller@10481000 {
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 3/8] dt-bindings: clock: samsung: convert Exynos5433 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos5433 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos5433-clock.txt | 507 -----------------
.../clock/samsung,exynos5433-clock.yaml | 524 ++++++++++++++++++
2 files changed, 524 insertions(+), 507 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
deleted file mode 100644
index 183c327a7d6b..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ /dev/null
@@ -1,507 +0,0 @@
-* Samsung Exynos5433 CMU (Clock Management Units)
-
-The Exynos5433 clock controller generates and supplies clock to various
-controllers within the Exynos5433 SoC.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
- which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
- domains and bus clocks.
- - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
- which generates clocks for LLI (Low Latency Interface) IP.
- - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
- which generates clocks for DRAM Memory Controller domain.
- - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
- which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
- - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
- which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
- - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
- which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
- which generates clocks for G2D/MDMA IPs.
- - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
- which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
- which generates clocks for Cortex-A5/BUS/AUDIO clocks.
- - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
- and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
- which generates global data buses clock and global peripheral buses clock.
- - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
- which generates clocks for 3D Graphics Engine IP.
- - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
- which generates clocks for GSCALER IPs.
- - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
- which generates clocks for Cortex-A53 Quad-core processor.
- - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
- which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
- L2 cache controller.
- - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
- which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
- - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
- which generates clocks for MFC(Multi-Format Codec) IP.
- - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
- which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
- - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
- which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
- - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
- which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
- IPs.
- - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
- which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
- - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
- which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-- clocks: list of the clock controller input clock identifiers,
- from common clock bindings. Please refer the next section
- to find the input clocks for a given controller.
-
-- clock-names: list of the clock controller input clock names,
- as described in clock-bindings.txt.
-
- Input clocks for top clock controller:
- - oscclk
- - sclk_mphy_pll
- - sclk_mfc_pll
- - sclk_bus_pll
-
- Input clocks for cpif clock controller:
- - oscclk
-
- Input clocks for mif clock controller:
- - oscclk
- - sclk_mphy_pll
-
- Input clocks for fsys clock controller:
- - oscclk
- - sclk_ufs_mphy
- - aclk_fsys_200
- - sclk_pcie_100_fsys
- - sclk_ufsunipro_fsys
- - sclk_mmc2_fsys
- - sclk_mmc1_fsys
- - sclk_mmc0_fsys
- - sclk_usbhost30_fsys
- - sclk_usbdrd30_fsys
-
- Input clocks for g2d clock controller:
- - oscclk
- - aclk_g2d_266
- - aclk_g2d_400
-
- Input clocks for disp clock controller:
- - oscclk
- - sclk_dsim1_disp
- - sclk_dsim0_disp
- - sclk_dsd_disp
- - sclk_decon_tv_eclk_disp
- - sclk_decon_vclk_disp
- - sclk_decon_eclk_disp
- - sclk_decon_tv_vclk_disp
- - aclk_disp_333
-
- Input clocks for audio clock controller:
- - oscclk
- - fout_aud_pll
-
- Input clocks for bus0 clock controller:
- - aclk_bus0_400
-
- Input clocks for bus1 clock controller:
- - aclk_bus1_400
-
- Input clocks for bus2 clock controller:
- - oscclk
- - aclk_bus2_400
-
- Input clocks for g3d clock controller:
- - oscclk
- - aclk_g3d_400
-
- Input clocks for gscl clock controller:
- - oscclk
- - aclk_gscl_111
- - aclk_gscl_333
-
- Input clocks for apollo clock controller:
- - oscclk
- - sclk_bus_pll_apollo
-
- Input clocks for atlas clock controller:
- - oscclk
- - sclk_bus_pll_atlas
-
- Input clocks for mscl clock controller:
- - oscclk
- - sclk_jpeg_mscl
- - aclk_mscl_400
-
- Input clocks for mfc clock controller:
- - oscclk
- - aclk_mfc_400
-
- Input clocks for hevc clock controller:
- - oscclk
- - aclk_hevc_400
-
- Input clocks for isp clock controller:
- - oscclk
- - aclk_isp_dis_400
- - aclk_isp_400
-
- Input clocks for cam0 clock controller:
- - oscclk
- - aclk_cam0_333
- - aclk_cam0_400
- - aclk_cam0_552
-
- Input clocks for cam1 clock controller:
- - oscclk
- - sclk_isp_uart_cam1
- - sclk_isp_spi1_cam1
- - sclk_isp_spi0_cam1
- - aclk_cam1_333
- - aclk_cam1_400
- - aclk_cam1_552
-
- Input clocks for imem clock controller:
- - oscclk
- - aclk_imem_sssx_266
- - aclk_imem_266
- - aclk_imem_200
-
-Optional properties:
- - power-domains: a phandle to respective power domain node as described by
- generic PM domain bindings (see power/power_domain.txt for more
- information).
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5433.h header and can be used in device
-tree sources.
-
-Example 1: Examples of 'oscclk' source clock node are listed below.
-
- xxti: xxti {
- compatible = "fixed-clock";
- clock-output-names = "oscclk";
- #clock-cells = <0>;
- };
-
-Example 2: Examples of clock controller nodes are listed below.
-
- cmu_top: clock-controller@10030000 {
- compatible = "samsung,exynos5433-cmu-top";
- reg = <0x10030000 0x0c04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_mphy_pll",
- "sclk_mfc_pll",
- "sclk_bus_pll";
- clocks = <&xxti>,
- <&cmu_cpif CLK_SCLK_MPHY_PLL>,
- <&cmu_mif CLK_SCLK_MFC_PLL>,
- <&cmu_mif CLK_SCLK_BUS_PLL>;
- };
-
- cmu_cpif: clock-controller@10fc0000 {
- compatible = "samsung,exynos5433-cmu-cpif";
- reg = <0x10fc0000 0x0c04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk";
- clocks = <&xxti>;
- };
-
- cmu_mif: clock-controller@105b0000 {
- compatible = "samsung,exynos5433-cmu-mif";
- reg = <0x105b0000 0x100c>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_mphy_pll";
- clocks = <&xxti>,
- <&cmu_cpif CLK_SCLK_MPHY_PLL>;
- };
-
- cmu_peric: clock-controller@14c80000 {
- compatible = "samsung,exynos5433-cmu-peric";
- reg = <0x14c80000 0x0b08>;
- #clock-cells = <1>;
- };
-
- cmu_peris: clock-controller@10040000 {
- compatible = "samsung,exynos5433-cmu-peris";
- reg = <0x10040000 0x0b20>;
- #clock-cells = <1>;
- };
-
- cmu_fsys: clock-controller@156e0000 {
- compatible = "samsung,exynos5433-cmu-fsys";
- reg = <0x156e0000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_ufs_mphy",
- "aclk_fsys_200",
- "sclk_pcie_100_fsys",
- "sclk_ufsunipro_fsys",
- "sclk_mmc2_fsys",
- "sclk_mmc1_fsys",
- "sclk_mmc0_fsys",
- "sclk_usbhost30_fsys",
- "sclk_usbdrd30_fsys";
- clocks = <&xxti>,
- <&cmu_cpif CLK_SCLK_UFS_MPHY>,
- <&cmu_top CLK_ACLK_FSYS_200>,
- <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
- <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
- <&cmu_top CLK_SCLK_MMC2_FSYS>,
- <&cmu_top CLK_SCLK_MMC1_FSYS>,
- <&cmu_top CLK_SCLK_MMC0_FSYS>,
- <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
- <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
- };
-
- cmu_g2d: clock-controller@12460000 {
- compatible = "samsung,exynos5433-cmu-g2d";
- reg = <0x12460000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_g2d_266",
- "aclk_g2d_400";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_G2D_266>,
- <&cmu_top CLK_ACLK_G2D_400>;
- power-domains = <&pd_g2d>;
- };
-
- cmu_disp: clock-controller@13b90000 {
- compatible = "samsung,exynos5433-cmu-disp";
- reg = <0x13b90000 0x0c04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_dsim1_disp",
- "sclk_dsim0_disp",
- "sclk_dsd_disp",
- "sclk_decon_tv_eclk_disp",
- "sclk_decon_vclk_disp",
- "sclk_decon_eclk_disp",
- "sclk_decon_tv_vclk_disp",
- "aclk_disp_333";
- clocks = <&xxti>,
- <&cmu_mif CLK_SCLK_DSIM1_DISP>,
- <&cmu_mif CLK_SCLK_DSIM0_DISP>,
- <&cmu_mif CLK_SCLK_DSD_DISP>,
- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
- <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
- <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
- <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
- <&cmu_mif CLK_ACLK_DISP_333>;
- power-domains = <&pd_disp>;
- };
-
- cmu_aud: clock-controller@114c0000 {
- compatible = "samsung,exynos5433-cmu-aud";
- reg = <0x114c0000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "fout_aud_pll";
- clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
- power-domains = <&pd_aud>;
- };
-
- cmu_bus0: clock-controller@13600000 {
- compatible = "samsung,exynos5433-cmu-bus0";
- reg = <0x13600000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "aclk_bus0_400";
- clocks = <&cmu_top CLK_ACLK_BUS0_400>;
- };
-
- cmu_bus1: clock-controller@14800000 {
- compatible = "samsung,exynos5433-cmu-bus1";
- reg = <0x14800000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "aclk_bus1_400";
- clocks = <&cmu_top CLK_ACLK_BUS1_400>;
- };
-
- cmu_bus2: clock-controller@13400000 {
- compatible = "samsung,exynos5433-cmu-bus2";
- reg = <0x13400000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_bus2_400";
- clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
- };
-
- cmu_g3d: clock-controller@14aa0000 {
- compatible = "samsung,exynos5433-cmu-g3d";
- reg = <0x14aa0000 0x1000>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_g3d_400";
- clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
- power-domains = <&pd_g3d>;
- };
-
- cmu_gscl: clock-controller@13cf0000 {
- compatible = "samsung,exynos5433-cmu-gscl";
- reg = <0x13cf0000 0x0b10>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_gscl_111",
- "aclk_gscl_333";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_GSCL_111>,
- <&cmu_top CLK_ACLK_GSCL_333>;
- power-domains = <&pd_gscl>;
- };
-
- cmu_apollo: clock-controller@11900000 {
- compatible = "samsung,exynos5433-cmu-apollo";
- reg = <0x11900000 0x1088>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "sclk_bus_pll_apollo";
- clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
- };
-
- cmu_atlas: clock-controller@11800000 {
- compatible = "samsung,exynos5433-cmu-atlas";
- reg = <0x11800000 0x1088>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "sclk_bus_pll_atlas";
- clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
- };
-
- cmu_mscl: clock-controller@105d0000 {
- compatible = "samsung,exynos5433-cmu-mscl";
- reg = <0x105d0000 0x0b10>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_jpeg_mscl",
- "aclk_mscl_400";
- clocks = <&xxti>,
- <&cmu_top CLK_SCLK_JPEG_MSCL>,
- <&cmu_top CLK_ACLK_MSCL_400>;
- power-domains = <&pd_mscl>;
- };
-
- cmu_mfc: clock-controller@15280000 {
- compatible = "samsung,exynos5433-cmu-mfc";
- reg = <0x15280000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_mfc_400";
- clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
- power-domains = <&pd_mfc>;
- };
-
- cmu_hevc: clock-controller@14f80000 {
- compatible = "samsung,exynos5433-cmu-hevc";
- reg = <0x14f80000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_hevc_400";
- clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
- power-domains = <&pd_hevc>;
- };
-
- cmu_isp: clock-controller@146d0000 {
- compatible = "samsung,exynos5433-cmu-isp";
- reg = <0x146d0000 0x0b0c>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_isp_dis_400",
- "aclk_isp_400";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_ISP_DIS_400>,
- <&cmu_top CLK_ACLK_ISP_400>;
- power-domains = <&pd_isp>;
- };
-
- cmu_cam0: clock-controller@120d0000 {
- compatible = "samsung,exynos5433-cmu-cam0";
- reg = <0x120d0000 0x0b0c>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_cam0_333",
- "aclk_cam0_400",
- "aclk_cam0_552";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_CAM0_333>,
- <&cmu_top CLK_ACLK_CAM0_400>,
- <&cmu_top CLK_ACLK_CAM0_552>;
- power-domains = <&pd_cam0>;
- };
-
- cmu_cam1: clock-controller@145d0000 {
- compatible = "samsung,exynos5433-cmu-cam1";
- reg = <0x145d0000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_isp_uart_cam1",
- "sclk_isp_spi1_cam1",
- "sclk_isp_spi0_cam1",
- "aclk_cam1_333",
- "aclk_cam1_400",
- "aclk_cam1_552";
- clocks = <&xxti>,
- <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
- <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
- <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
- <&cmu_top CLK_ACLK_CAM1_333>,
- <&cmu_top CLK_ACLK_CAM1_400>,
- <&cmu_top CLK_ACLK_CAM1_552>;
- power-domains = <&pd_cam1>;
- };
-
- cmu_imem: clock-controller@11060000 {
- compatible = "samsung,exynos5433-cmu-imem";
- reg = <0x11060000 0x1000>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_imem_sssx_266",
- "aclk_imem_266",
- "aclk_imem_200";
- clocks = <&xxti>,
- <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
- <&cmu_top CLK_DIV_ACLK_IMEM_266>,
- <&cmu_top CLK_DIV_ACLK_IMEM_200>;
- };
-
-Example 3: UART controller node that consumes the clock generated by the clock
- controller.
-
- serial_0: serial@14c10000 {
- compatible = "samsung,exynos5433-uart";
- reg = <0x14C10000 0x100>;
- interrupts = <0 421 0>;
- clocks = <&cmu_peric CLK_PCLK_UART0>,
- <&cmu_peric CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_bus>;
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
new file mode 100644
index 000000000000..edd1b4ac4334
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
@@ -0,0 +1,524 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5433 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "oscclk" - PLL input clock from XXTI
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos5433.h header.
+
+properties:
+ compatible:
+ enum:
+ # CMU_TOP which generates clocks for
+ # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
+ # clocks
+ - samsung,exynos5433-cmu-top
+ # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
+ - samsung,exynos5433-cmu-cpif
+ # CMU_MIF which generates clocks for DRAM Memory Controller domain
+ - samsung,exynos5433-cmu-mif
+ # CMU_PERIC which generates clocks for
+ # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
+ - samsung,exynos5433-cmu-peric
+ # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
+ - samsung,exynos5433-cmu-peris
+ # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
+ - samsung,exynos5433-cmu-fsys
+ - samsung,exynos5433-cmu-g2d
+ # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
+ - samsung,exynos5433-cmu-disp
+ - samsung,exynos5433-cmu-aud
+ - samsung,exynos5433-cmu-bus0
+ - samsung,exynos5433-cmu-bus1
+ - samsung,exynos5433-cmu-bus2
+ - samsung,exynos5433-cmu-g3d
+ - samsung,exynos5433-cmu-gscl
+ - samsung,exynos5433-cmu-apollo
+ # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
+ # CoreSight and L2 cache controller
+ - samsung,exynos5433-cmu-atlas
+ # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
+ # JPEG IPs
+ - samsung,exynos5433-cmu-mscl
+ - samsung,exynos5433-cmu-mfc
+ - samsung,exynos5433-cmu-hevc
+ # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
+ - samsung,exynos5433-cmu-isp
+ # CMU_CAM0 which generates clocks for
+ # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
+ - samsung,exynos5433-cmu-cam0
+ # CMU_CAM1 which generates clocks for
+ # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
+ - samsung,exynos5433-cmu-cam1
+ # CMU_IMEM which generates clocks for SSS (Security SubSystem) and
+ # SlimSSS IPs
+ - samsung,exynos5433-cmu-imem
+
+ clocks:
+ minItems: 1
+ maxItems: 10
+
+ clock-names:
+ minItems: 1
+ maxItems: 10
+
+ "#clock-cells":
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-top
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_mphy_pll
+ - const: sclk_mfc_pll
+ - const: sclk_bus_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-cpif
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: oscclk
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-mif
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_mphy_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-fsys
+ then:
+ properties:
+ clocks:
+ minItems: 10
+ maxItems: 10
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_ufs_mphy
+ - const: aclk_fsys_200
+ - const: sclk_pcie_100_fsys
+ - const: sclk_ufsunipro_fsys
+ - const: sclk_mmc2_fsys
+ - const: sclk_mmc1_fsys
+ - const: sclk_mmc0_fsys
+ - const: sclk_usbhost30_fsys
+ - const: sclk_usbdrd30_fsys
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-g2d
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_g2d_266
+ - const: aclk_g2d_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-disp
+ then:
+ properties:
+ clocks:
+ minItems: 9
+ maxItems: 9
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_dsim1_disp
+ - const: sclk_dsim0_disp
+ - const: sclk_dsd_disp
+ - const: sclk_decon_tv_eclk_disp
+ - const: sclk_decon_vclk_disp
+ - const: sclk_decon_eclk_disp
+ - const: sclk_decon_tv_vclk_disp
+ - const: aclk_disp_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-aud
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: fout_aud_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-bus0
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: aclk_bus0_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-bus1
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: aclk_bus1_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-bus2
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_bus2_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-g3d
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_g3d_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-gscl
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_gscl_111
+ - const: aclk_gscl_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-apollo
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_bus_pll_apollo
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-atlas
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_bus_pll_atlas
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-mscl
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_jpeg_mscl
+ - const: aclk_mscl_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-mfc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_mfc_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-hevc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_hevc_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-isp
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_isp_dis_400
+ - const: aclk_isp_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-cam0
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_cam0_333
+ - const: aclk_cam0_400
+ - const: aclk_cam0_552
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-cam1
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_isp_uart_cam1
+ - const: sclk_isp_spi1_cam1
+ - const: sclk_isp_spi0_cam1
+ - const: aclk_cam1_333
+ - const: aclk_cam1_400
+ - const: aclk_cam1_552
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-imem
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_imem_sssx_266
+ - const: aclk_imem_266
+ - const: aclk_imem_200
+ required:
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ xxti: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "oscclk";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ clock-controller@10030000 {
+ compatible = "samsung,exynos5433-cmu-top";
+ reg = <0x10030000 0x1000>;
+ #clock-cells = <1>;
+
+ clock-names = "oscclk",
+ "sclk_mphy_pll",
+ "sclk_mfc_pll",
+ "sclk_bus_pll";
+ clocks = <&xxti>,
+ <&cmu_cpif CLK_SCLK_MPHY_PLL>,
+ <&cmu_mif CLK_SCLK_MFC_PLL>,
+ <&cmu_mif CLK_SCLK_BUS_PLL>;
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 3/8] dt-bindings: clock: samsung: convert Exynos5433 to dtschema
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos5433 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos5433-clock.txt | 507 -----------------
.../clock/samsung,exynos5433-clock.yaml | 524 ++++++++++++++++++
2 files changed, 524 insertions(+), 507 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
deleted file mode 100644
index 183c327a7d6b..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ /dev/null
@@ -1,507 +0,0 @@
-* Samsung Exynos5433 CMU (Clock Management Units)
-
-The Exynos5433 clock controller generates and supplies clock to various
-controllers within the Exynos5433 SoC.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
- which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
- domains and bus clocks.
- - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
- which generates clocks for LLI (Low Latency Interface) IP.
- - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
- which generates clocks for DRAM Memory Controller domain.
- - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
- which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
- - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
- which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
- - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
- which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
- - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
- which generates clocks for G2D/MDMA IPs.
- - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
- which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
- - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
- which generates clocks for Cortex-A5/BUS/AUDIO clocks.
- - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
- and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
- which generates global data buses clock and global peripheral buses clock.
- - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
- which generates clocks for 3D Graphics Engine IP.
- - "samsung,exynos5433-cmu-gscl" - clock controller compatible for CMU_GSCL
- which generates clocks for GSCALER IPs.
- - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
- which generates clocks for Cortex-A53 Quad-core processor.
- - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
- which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
- L2 cache controller.
- - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
- which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
- - "samsung,exynos5433-cmu-mfc" - clock controller compatible for CMU_MFC
- which generates clocks for MFC(Multi-Format Codec) IP.
- - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
- which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
- - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
- which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
- - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
- which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
- IPs.
- - "samsung,exynos5433-cmu-cam1" - clock controller compatible for CMU_CAM1
- which generates clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs.
- - "samsung,exynos5433-cmu-imem" - clock controller compatible for CMU_IMEM
- which generates clocks for SSS (Security SubSystem) and SlimSSS IPs.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-- clocks: list of the clock controller input clock identifiers,
- from common clock bindings. Please refer the next section
- to find the input clocks for a given controller.
-
-- clock-names: list of the clock controller input clock names,
- as described in clock-bindings.txt.
-
- Input clocks for top clock controller:
- - oscclk
- - sclk_mphy_pll
- - sclk_mfc_pll
- - sclk_bus_pll
-
- Input clocks for cpif clock controller:
- - oscclk
-
- Input clocks for mif clock controller:
- - oscclk
- - sclk_mphy_pll
-
- Input clocks for fsys clock controller:
- - oscclk
- - sclk_ufs_mphy
- - aclk_fsys_200
- - sclk_pcie_100_fsys
- - sclk_ufsunipro_fsys
- - sclk_mmc2_fsys
- - sclk_mmc1_fsys
- - sclk_mmc0_fsys
- - sclk_usbhost30_fsys
- - sclk_usbdrd30_fsys
-
- Input clocks for g2d clock controller:
- - oscclk
- - aclk_g2d_266
- - aclk_g2d_400
-
- Input clocks for disp clock controller:
- - oscclk
- - sclk_dsim1_disp
- - sclk_dsim0_disp
- - sclk_dsd_disp
- - sclk_decon_tv_eclk_disp
- - sclk_decon_vclk_disp
- - sclk_decon_eclk_disp
- - sclk_decon_tv_vclk_disp
- - aclk_disp_333
-
- Input clocks for audio clock controller:
- - oscclk
- - fout_aud_pll
-
- Input clocks for bus0 clock controller:
- - aclk_bus0_400
-
- Input clocks for bus1 clock controller:
- - aclk_bus1_400
-
- Input clocks for bus2 clock controller:
- - oscclk
- - aclk_bus2_400
-
- Input clocks for g3d clock controller:
- - oscclk
- - aclk_g3d_400
-
- Input clocks for gscl clock controller:
- - oscclk
- - aclk_gscl_111
- - aclk_gscl_333
-
- Input clocks for apollo clock controller:
- - oscclk
- - sclk_bus_pll_apollo
-
- Input clocks for atlas clock controller:
- - oscclk
- - sclk_bus_pll_atlas
-
- Input clocks for mscl clock controller:
- - oscclk
- - sclk_jpeg_mscl
- - aclk_mscl_400
-
- Input clocks for mfc clock controller:
- - oscclk
- - aclk_mfc_400
-
- Input clocks for hevc clock controller:
- - oscclk
- - aclk_hevc_400
-
- Input clocks for isp clock controller:
- - oscclk
- - aclk_isp_dis_400
- - aclk_isp_400
-
- Input clocks for cam0 clock controller:
- - oscclk
- - aclk_cam0_333
- - aclk_cam0_400
- - aclk_cam0_552
-
- Input clocks for cam1 clock controller:
- - oscclk
- - sclk_isp_uart_cam1
- - sclk_isp_spi1_cam1
- - sclk_isp_spi0_cam1
- - aclk_cam1_333
- - aclk_cam1_400
- - aclk_cam1_552
-
- Input clocks for imem clock controller:
- - oscclk
- - aclk_imem_sssx_266
- - aclk_imem_266
- - aclk_imem_200
-
-Optional properties:
- - power-domains: a phandle to respective power domain node as described by
- generic PM domain bindings (see power/power_domain.txt for more
- information).
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5433.h header and can be used in device
-tree sources.
-
-Example 1: Examples of 'oscclk' source clock node are listed below.
-
- xxti: xxti {
- compatible = "fixed-clock";
- clock-output-names = "oscclk";
- #clock-cells = <0>;
- };
-
-Example 2: Examples of clock controller nodes are listed below.
-
- cmu_top: clock-controller@10030000 {
- compatible = "samsung,exynos5433-cmu-top";
- reg = <0x10030000 0x0c04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_mphy_pll",
- "sclk_mfc_pll",
- "sclk_bus_pll";
- clocks = <&xxti>,
- <&cmu_cpif CLK_SCLK_MPHY_PLL>,
- <&cmu_mif CLK_SCLK_MFC_PLL>,
- <&cmu_mif CLK_SCLK_BUS_PLL>;
- };
-
- cmu_cpif: clock-controller@10fc0000 {
- compatible = "samsung,exynos5433-cmu-cpif";
- reg = <0x10fc0000 0x0c04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk";
- clocks = <&xxti>;
- };
-
- cmu_mif: clock-controller@105b0000 {
- compatible = "samsung,exynos5433-cmu-mif";
- reg = <0x105b0000 0x100c>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_mphy_pll";
- clocks = <&xxti>,
- <&cmu_cpif CLK_SCLK_MPHY_PLL>;
- };
-
- cmu_peric: clock-controller@14c80000 {
- compatible = "samsung,exynos5433-cmu-peric";
- reg = <0x14c80000 0x0b08>;
- #clock-cells = <1>;
- };
-
- cmu_peris: clock-controller@10040000 {
- compatible = "samsung,exynos5433-cmu-peris";
- reg = <0x10040000 0x0b20>;
- #clock-cells = <1>;
- };
-
- cmu_fsys: clock-controller@156e0000 {
- compatible = "samsung,exynos5433-cmu-fsys";
- reg = <0x156e0000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_ufs_mphy",
- "aclk_fsys_200",
- "sclk_pcie_100_fsys",
- "sclk_ufsunipro_fsys",
- "sclk_mmc2_fsys",
- "sclk_mmc1_fsys",
- "sclk_mmc0_fsys",
- "sclk_usbhost30_fsys",
- "sclk_usbdrd30_fsys";
- clocks = <&xxti>,
- <&cmu_cpif CLK_SCLK_UFS_MPHY>,
- <&cmu_top CLK_ACLK_FSYS_200>,
- <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
- <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
- <&cmu_top CLK_SCLK_MMC2_FSYS>,
- <&cmu_top CLK_SCLK_MMC1_FSYS>,
- <&cmu_top CLK_SCLK_MMC0_FSYS>,
- <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
- <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
- };
-
- cmu_g2d: clock-controller@12460000 {
- compatible = "samsung,exynos5433-cmu-g2d";
- reg = <0x12460000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_g2d_266",
- "aclk_g2d_400";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_G2D_266>,
- <&cmu_top CLK_ACLK_G2D_400>;
- power-domains = <&pd_g2d>;
- };
-
- cmu_disp: clock-controller@13b90000 {
- compatible = "samsung,exynos5433-cmu-disp";
- reg = <0x13b90000 0x0c04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_dsim1_disp",
- "sclk_dsim0_disp",
- "sclk_dsd_disp",
- "sclk_decon_tv_eclk_disp",
- "sclk_decon_vclk_disp",
- "sclk_decon_eclk_disp",
- "sclk_decon_tv_vclk_disp",
- "aclk_disp_333";
- clocks = <&xxti>,
- <&cmu_mif CLK_SCLK_DSIM1_DISP>,
- <&cmu_mif CLK_SCLK_DSIM0_DISP>,
- <&cmu_mif CLK_SCLK_DSD_DISP>,
- <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
- <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
- <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
- <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
- <&cmu_mif CLK_ACLK_DISP_333>;
- power-domains = <&pd_disp>;
- };
-
- cmu_aud: clock-controller@114c0000 {
- compatible = "samsung,exynos5433-cmu-aud";
- reg = <0x114c0000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "fout_aud_pll";
- clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
- power-domains = <&pd_aud>;
- };
-
- cmu_bus0: clock-controller@13600000 {
- compatible = "samsung,exynos5433-cmu-bus0";
- reg = <0x13600000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "aclk_bus0_400";
- clocks = <&cmu_top CLK_ACLK_BUS0_400>;
- };
-
- cmu_bus1: clock-controller@14800000 {
- compatible = "samsung,exynos5433-cmu-bus1";
- reg = <0x14800000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "aclk_bus1_400";
- clocks = <&cmu_top CLK_ACLK_BUS1_400>;
- };
-
- cmu_bus2: clock-controller@13400000 {
- compatible = "samsung,exynos5433-cmu-bus2";
- reg = <0x13400000 0x0b04>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_bus2_400";
- clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
- };
-
- cmu_g3d: clock-controller@14aa0000 {
- compatible = "samsung,exynos5433-cmu-g3d";
- reg = <0x14aa0000 0x1000>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_g3d_400";
- clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
- power-domains = <&pd_g3d>;
- };
-
- cmu_gscl: clock-controller@13cf0000 {
- compatible = "samsung,exynos5433-cmu-gscl";
- reg = <0x13cf0000 0x0b10>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_gscl_111",
- "aclk_gscl_333";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_GSCL_111>,
- <&cmu_top CLK_ACLK_GSCL_333>;
- power-domains = <&pd_gscl>;
- };
-
- cmu_apollo: clock-controller@11900000 {
- compatible = "samsung,exynos5433-cmu-apollo";
- reg = <0x11900000 0x1088>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "sclk_bus_pll_apollo";
- clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
- };
-
- cmu_atlas: clock-controller@11800000 {
- compatible = "samsung,exynos5433-cmu-atlas";
- reg = <0x11800000 0x1088>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "sclk_bus_pll_atlas";
- clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
- };
-
- cmu_mscl: clock-controller@105d0000 {
- compatible = "samsung,exynos5433-cmu-mscl";
- reg = <0x105d0000 0x0b10>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_jpeg_mscl",
- "aclk_mscl_400";
- clocks = <&xxti>,
- <&cmu_top CLK_SCLK_JPEG_MSCL>,
- <&cmu_top CLK_ACLK_MSCL_400>;
- power-domains = <&pd_mscl>;
- };
-
- cmu_mfc: clock-controller@15280000 {
- compatible = "samsung,exynos5433-cmu-mfc";
- reg = <0x15280000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_mfc_400";
- clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
- power-domains = <&pd_mfc>;
- };
-
- cmu_hevc: clock-controller@14f80000 {
- compatible = "samsung,exynos5433-cmu-hevc";
- reg = <0x14f80000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk", "aclk_hevc_400";
- clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
- power-domains = <&pd_hevc>;
- };
-
- cmu_isp: clock-controller@146d0000 {
- compatible = "samsung,exynos5433-cmu-isp";
- reg = <0x146d0000 0x0b0c>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_isp_dis_400",
- "aclk_isp_400";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_ISP_DIS_400>,
- <&cmu_top CLK_ACLK_ISP_400>;
- power-domains = <&pd_isp>;
- };
-
- cmu_cam0: clock-controller@120d0000 {
- compatible = "samsung,exynos5433-cmu-cam0";
- reg = <0x120d0000 0x0b0c>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_cam0_333",
- "aclk_cam0_400",
- "aclk_cam0_552";
- clocks = <&xxti>,
- <&cmu_top CLK_ACLK_CAM0_333>,
- <&cmu_top CLK_ACLK_CAM0_400>,
- <&cmu_top CLK_ACLK_CAM0_552>;
- power-domains = <&pd_cam0>;
- };
-
- cmu_cam1: clock-controller@145d0000 {
- compatible = "samsung,exynos5433-cmu-cam1";
- reg = <0x145d0000 0x0b08>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "sclk_isp_uart_cam1",
- "sclk_isp_spi1_cam1",
- "sclk_isp_spi0_cam1",
- "aclk_cam1_333",
- "aclk_cam1_400",
- "aclk_cam1_552";
- clocks = <&xxti>,
- <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
- <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
- <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
- <&cmu_top CLK_ACLK_CAM1_333>,
- <&cmu_top CLK_ACLK_CAM1_400>,
- <&cmu_top CLK_ACLK_CAM1_552>;
- power-domains = <&pd_cam1>;
- };
-
- cmu_imem: clock-controller@11060000 {
- compatible = "samsung,exynos5433-cmu-imem";
- reg = <0x11060000 0x1000>;
- #clock-cells = <1>;
-
- clock-names = "oscclk",
- "aclk_imem_sssx_266",
- "aclk_imem_266",
- "aclk_imem_200";
- clocks = <&xxti>,
- <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
- <&cmu_top CLK_DIV_ACLK_IMEM_266>,
- <&cmu_top CLK_DIV_ACLK_IMEM_200>;
- };
-
-Example 3: UART controller node that consumes the clock generated by the clock
- controller.
-
- serial_0: serial@14c10000 {
- compatible = "samsung,exynos5433-uart";
- reg = <0x14C10000 0x100>;
- interrupts = <0 421 0>;
- clocks = <&cmu_peric CLK_PCLK_UART0>,
- <&cmu_peric CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_bus>;
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
new file mode 100644
index 000000000000..edd1b4ac4334
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
@@ -0,0 +1,524 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5433-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5433 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "oscclk" - PLL input clock from XXTI
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos5433.h header.
+
+properties:
+ compatible:
+ enum:
+ # CMU_TOP which generates clocks for
+ # IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS domains and bus
+ # clocks
+ - samsung,exynos5433-cmu-top
+ # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP
+ - samsung,exynos5433-cmu-cpif
+ # CMU_MIF which generates clocks for DRAM Memory Controller domain
+ - samsung,exynos5433-cmu-mif
+ # CMU_PERIC which generates clocks for
+ # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
+ - samsung,exynos5433-cmu-peric
+ # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
+ - samsung,exynos5433-cmu-peris
+ # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
+ - samsung,exynos5433-cmu-fsys
+ - samsung,exynos5433-cmu-g2d
+ # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
+ - samsung,exynos5433-cmu-disp
+ - samsung,exynos5433-cmu-aud
+ - samsung,exynos5433-cmu-bus0
+ - samsung,exynos5433-cmu-bus1
+ - samsung,exynos5433-cmu-bus2
+ - samsung,exynos5433-cmu-g3d
+ - samsung,exynos5433-cmu-gscl
+ - samsung,exynos5433-cmu-apollo
+ # CMU_ATLAS which generates clocks for Cortex-A57 Quad-core processor,
+ # CoreSight and L2 cache controller
+ - samsung,exynos5433-cmu-atlas
+ # CMU_MSCL which generates clocks for M2M (Memory to Memory) scaler and
+ # JPEG IPs
+ - samsung,exynos5433-cmu-mscl
+ - samsung,exynos5433-cmu-mfc
+ - samsung,exynos5433-cmu-hevc
+ # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
+ - samsung,exynos5433-cmu-isp
+ # CMU_CAM0 which generates clocks for
+ # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
+ - samsung,exynos5433-cmu-cam0
+ # CMU_CAM1 which generates clocks for
+ # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
+ - samsung,exynos5433-cmu-cam1
+ # CMU_IMEM which generates clocks for SSS (Security SubSystem) and
+ # SlimSSS IPs
+ - samsung,exynos5433-cmu-imem
+
+ clocks:
+ minItems: 1
+ maxItems: 10
+
+ clock-names:
+ minItems: 1
+ maxItems: 10
+
+ "#clock-cells":
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-top
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_mphy_pll
+ - const: sclk_mfc_pll
+ - const: sclk_bus_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-cpif
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: oscclk
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-mif
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_mphy_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-fsys
+ then:
+ properties:
+ clocks:
+ minItems: 10
+ maxItems: 10
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_ufs_mphy
+ - const: aclk_fsys_200
+ - const: sclk_pcie_100_fsys
+ - const: sclk_ufsunipro_fsys
+ - const: sclk_mmc2_fsys
+ - const: sclk_mmc1_fsys
+ - const: sclk_mmc0_fsys
+ - const: sclk_usbhost30_fsys
+ - const: sclk_usbdrd30_fsys
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-g2d
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_g2d_266
+ - const: aclk_g2d_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-disp
+ then:
+ properties:
+ clocks:
+ minItems: 9
+ maxItems: 9
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_dsim1_disp
+ - const: sclk_dsim0_disp
+ - const: sclk_dsd_disp
+ - const: sclk_decon_tv_eclk_disp
+ - const: sclk_decon_vclk_disp
+ - const: sclk_decon_eclk_disp
+ - const: sclk_decon_tv_vclk_disp
+ - const: aclk_disp_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-aud
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: fout_aud_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-bus0
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: aclk_bus0_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-bus1
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: aclk_bus1_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-bus2
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_bus2_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-g3d
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_g3d_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-gscl
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_gscl_111
+ - const: aclk_gscl_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-apollo
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_bus_pll_apollo
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-atlas
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_bus_pll_atlas
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-mscl
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_jpeg_mscl
+ - const: aclk_mscl_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-mfc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_mfc_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-hevc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_hevc_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-isp
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_isp_dis_400
+ - const: aclk_isp_400
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-cam0
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_cam0_333
+ - const: aclk_cam0_400
+ - const: aclk_cam0_552
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-cam1
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: oscclk
+ - const: sclk_isp_uart_cam1
+ - const: sclk_isp_spi1_cam1
+ - const: sclk_isp_spi0_cam1
+ - const: aclk_cam1_333
+ - const: aclk_cam1_400
+ - const: aclk_cam1_552
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-cmu-imem
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: oscclk
+ - const: aclk_imem_sssx_266
+ - const: aclk_imem_266
+ - const: aclk_imem_200
+ required:
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ xxti: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "oscclk";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ clock-controller@10030000 {
+ compatible = "samsung,exynos5433-cmu-top";
+ reg = <0x10030000 0x1000>;
+ #clock-cells = <1>;
+
+ clock-names = "oscclk",
+ "sclk_mphy_pll",
+ "sclk_mfc_pll",
+ "sclk_bus_pll";
+ clocks = <&xxti>,
+ <&cmu_cpif CLK_SCLK_MPHY_PLL>,
+ <&cmu_mif CLK_SCLK_MFC_PLL>,
+ <&cmu_mif CLK_SCLK_BUS_PLL>;
+ };
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 4/8] dt-bindings: clock: samsung: convert Exynos7 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos7 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos7-clock.txt | 108 -------
.../bindings/clock/samsung,exynos7-clock.yaml | 269 ++++++++++++++++++
2 files changed, 269 insertions(+), 108 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
deleted file mode 100644
index 6bf1e7493f61..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ /dev/null
@@ -1,108 +0,0 @@
-* Samsung Exynos7 Clock Controller
-
-Exynos7 clock controller has various blocks which are instantiated
-independently from the device-tree. These clock controllers
-generate and supply clocks to various hardware blocks within
-the SoC.
-
-Each clock is assigned an identifier and client nodes can use
-this identifier to specify the clock which they consume. All
-available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos7-clk.h header and can be used in
-device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It
-is expected that they are defined using standard clock bindings
-with following clock-output-names:
-
- - "fin_pll" - PLL input clock from XXTI
-
-Required Properties for Clock Controller:
-
- - compatible: clock controllers will use one of the following
- compatible strings to indicate the clock controller
- functionality.
-
- - "samsung,exynos7-clock-topc"
- - "samsung,exynos7-clock-top0"
- - "samsung,exynos7-clock-top1"
- - "samsung,exynos7-clock-ccore"
- - "samsung,exynos7-clock-peric0"
- - "samsung,exynos7-clock-peric1"
- - "samsung,exynos7-clock-peris"
- - "samsung,exynos7-clock-fsys0"
- - "samsung,exynos7-clock-fsys1"
- - "samsung,exynos7-clock-mscl"
- - "samsung,exynos7-clock-aud"
-
- - reg: physical base address of the controller and the length of
- memory mapped region.
-
- - #clock-cells: should be 1.
-
- - clocks: list of clock identifiers which are fed as the input to
- the given clock controller. Please refer the next section to
- find the input clocks for a given controller.
-
-- clock-names: list of names of clocks which are fed as the input
- to the given clock controller.
-
-Input clocks for top0 clock controller:
- - fin_pll
- - dout_sclk_bus0_pll
- - dout_sclk_bus1_pll
- - dout_sclk_cc_pll
- - dout_sclk_mfc_pll
- - dout_sclk_aud_pll
-
-Input clocks for top1 clock controller:
- - fin_pll
- - dout_sclk_bus0_pll
- - dout_sclk_bus1_pll
- - dout_sclk_cc_pll
- - dout_sclk_mfc_pll
-
-Input clocks for ccore clock controller:
- - fin_pll
- - dout_aclk_ccore_133
-
-Input clocks for peric0 clock controller:
- - fin_pll
- - dout_aclk_peric0_66
- - sclk_uart0
-
-Input clocks for peric1 clock controller:
- - fin_pll
- - dout_aclk_peric1_66
- - sclk_uart1
- - sclk_uart2
- - sclk_uart3
- - sclk_spi0
- - sclk_spi1
- - sclk_spi2
- - sclk_spi3
- - sclk_spi4
- - sclk_i2s1
- - sclk_pcm1
- - sclk_spdif
-
-Input clocks for peris clock controller:
- - fin_pll
- - dout_aclk_peris_66
-
-Input clocks for fsys0 clock controller:
- - fin_pll
- - dout_aclk_fsys0_200
- - dout_sclk_mmc2
-
-Input clocks for fsys1 clock controller:
- - fin_pll
- - dout_aclk_fsys1_200
- - dout_sclk_mmc0
- - dout_sclk_mmc1
-
-Input clocks for aud clock controller:
- - fin_pll
- - fout_aud_pll
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
new file mode 100644
index 000000000000..f3fa6c7ef48b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
@@ -0,0 +1,269 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "fin_pll" - PLL input clock from XXTI
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos7-clk.h header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos7-clock-topc
+ - samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-ccore
+ - samsung,exynos7-clock-peric0
+ - samsung,exynos7-clock-peric1
+ - samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
+ - samsung,exynos7-clock-mscl
+ - samsung,exynos7-clock-aud
+
+ clocks:
+ minItems: 1
+ maxItems: 13
+
+ clock-names:
+ minItems: 1
+ maxItems: 13
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-top0
+ then:
+ properties:
+ clocks:
+ minItems: 6
+ maxItems: 6
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_sclk_bus0_pll
+ - const: dout_sclk_bus1_pll
+ - const: dout_sclk_cc_pll
+ - const: dout_sclk_mfc_pll
+ - const: dout_sclk_aud_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-top1
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_sclk_bus0_pll
+ - const: dout_sclk_bus1_pll
+ - const: dout_sclk_cc_pll
+ - const: dout_sclk_mfc_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-ccore
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_ccore_133
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-peric0
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_peric0_66
+ - const: sclk_uart0
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-peric1
+ then:
+ properties:
+ clocks:
+ minItems: 13
+ maxItems: 13
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_peric1_66
+ - const: sclk_uart1
+ - const: sclk_uart2
+ - const: sclk_uart3
+ - const: sclk_spi0
+ - const: sclk_spi1
+ - const: sclk_spi2
+ - const: sclk_spi3
+ - const: sclk_spi4
+ - const: sclk_i2s1
+ - const: sclk_pcm1
+ - const: sclk_spdif
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-peris
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_peris_66
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-fsys0
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_fsys0_200
+ - const: dout_sclk_mmc2
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-fsys1
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_fsys1_200
+ - const: dout_sclk_mmc0
+ - const: dout_sclk_mmc1
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-aud
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: fout_aud_pll
+ required:
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7-clk.h>
+
+ fin_pll: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ clock-controller@105e0000 {
+ compatible = "samsung,exynos7-clock-top1";
+ reg = <0x105e0000 0xb000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_topc DOUT_SCLK_BUS0_PLL>,
+ <&clock_topc DOUT_SCLK_BUS1_PLL>,
+ <&clock_topc DOUT_SCLK_CC_PLL>,
+ <&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll",
+ "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll",
+ "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 4/8] dt-bindings: clock: samsung: convert Exynos7 to dtschema
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos7 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos7-clock.txt | 108 -------
.../bindings/clock/samsung,exynos7-clock.yaml | 269 ++++++++++++++++++
2 files changed, 269 insertions(+), 108 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
deleted file mode 100644
index 6bf1e7493f61..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ /dev/null
@@ -1,108 +0,0 @@
-* Samsung Exynos7 Clock Controller
-
-Exynos7 clock controller has various blocks which are instantiated
-independently from the device-tree. These clock controllers
-generate and supply clocks to various hardware blocks within
-the SoC.
-
-Each clock is assigned an identifier and client nodes can use
-this identifier to specify the clock which they consume. All
-available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos7-clk.h header and can be used in
-device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It
-is expected that they are defined using standard clock bindings
-with following clock-output-names:
-
- - "fin_pll" - PLL input clock from XXTI
-
-Required Properties for Clock Controller:
-
- - compatible: clock controllers will use one of the following
- compatible strings to indicate the clock controller
- functionality.
-
- - "samsung,exynos7-clock-topc"
- - "samsung,exynos7-clock-top0"
- - "samsung,exynos7-clock-top1"
- - "samsung,exynos7-clock-ccore"
- - "samsung,exynos7-clock-peric0"
- - "samsung,exynos7-clock-peric1"
- - "samsung,exynos7-clock-peris"
- - "samsung,exynos7-clock-fsys0"
- - "samsung,exynos7-clock-fsys1"
- - "samsung,exynos7-clock-mscl"
- - "samsung,exynos7-clock-aud"
-
- - reg: physical base address of the controller and the length of
- memory mapped region.
-
- - #clock-cells: should be 1.
-
- - clocks: list of clock identifiers which are fed as the input to
- the given clock controller. Please refer the next section to
- find the input clocks for a given controller.
-
-- clock-names: list of names of clocks which are fed as the input
- to the given clock controller.
-
-Input clocks for top0 clock controller:
- - fin_pll
- - dout_sclk_bus0_pll
- - dout_sclk_bus1_pll
- - dout_sclk_cc_pll
- - dout_sclk_mfc_pll
- - dout_sclk_aud_pll
-
-Input clocks for top1 clock controller:
- - fin_pll
- - dout_sclk_bus0_pll
- - dout_sclk_bus1_pll
- - dout_sclk_cc_pll
- - dout_sclk_mfc_pll
-
-Input clocks for ccore clock controller:
- - fin_pll
- - dout_aclk_ccore_133
-
-Input clocks for peric0 clock controller:
- - fin_pll
- - dout_aclk_peric0_66
- - sclk_uart0
-
-Input clocks for peric1 clock controller:
- - fin_pll
- - dout_aclk_peric1_66
- - sclk_uart1
- - sclk_uart2
- - sclk_uart3
- - sclk_spi0
- - sclk_spi1
- - sclk_spi2
- - sclk_spi3
- - sclk_spi4
- - sclk_i2s1
- - sclk_pcm1
- - sclk_spdif
-
-Input clocks for peris clock controller:
- - fin_pll
- - dout_aclk_peris_66
-
-Input clocks for fsys0 clock controller:
- - fin_pll
- - dout_aclk_fsys0_200
- - dout_sclk_mmc2
-
-Input clocks for fsys1 clock controller:
- - fin_pll
- - dout_aclk_fsys1_200
- - dout_sclk_mmc0
- - dout_sclk_mmc1
-
-Input clocks for aud clock controller:
- - fin_pll
- - fout_aud_pll
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
new file mode 100644
index 000000000000..f3fa6c7ef48b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
@@ -0,0 +1,269 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "fin_pll" - PLL input clock from XXTI
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos7-clk.h header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos7-clock-topc
+ - samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-top1
+ - samsung,exynos7-clock-ccore
+ - samsung,exynos7-clock-peric0
+ - samsung,exynos7-clock-peric1
+ - samsung,exynos7-clock-peris
+ - samsung,exynos7-clock-fsys0
+ - samsung,exynos7-clock-fsys1
+ - samsung,exynos7-clock-mscl
+ - samsung,exynos7-clock-aud
+
+ clocks:
+ minItems: 1
+ maxItems: 13
+
+ clock-names:
+ minItems: 1
+ maxItems: 13
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-top0
+ then:
+ properties:
+ clocks:
+ minItems: 6
+ maxItems: 6
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_sclk_bus0_pll
+ - const: dout_sclk_bus1_pll
+ - const: dout_sclk_cc_pll
+ - const: dout_sclk_mfc_pll
+ - const: dout_sclk_aud_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-top1
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_sclk_bus0_pll
+ - const: dout_sclk_bus1_pll
+ - const: dout_sclk_cc_pll
+ - const: dout_sclk_mfc_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-ccore
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_ccore_133
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-peric0
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_peric0_66
+ - const: sclk_uart0
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-peric1
+ then:
+ properties:
+ clocks:
+ minItems: 13
+ maxItems: 13
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_peric1_66
+ - const: sclk_uart1
+ - const: sclk_uart2
+ - const: sclk_uart3
+ - const: sclk_spi0
+ - const: sclk_spi1
+ - const: sclk_spi2
+ - const: sclk_spi3
+ - const: sclk_spi4
+ - const: sclk_i2s1
+ - const: sclk_pcm1
+ - const: sclk_spdif
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-peris
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_peris_66
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-fsys0
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_fsys0_200
+ - const: dout_sclk_mmc2
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-fsys1
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_fsys1_200
+ - const: dout_sclk_mmc0
+ - const: dout_sclk_mmc1
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7-clock-aud
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: fout_aud_pll
+ required:
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos7-clk.h>
+
+ fin_pll: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ clock-controller@105e0000 {
+ compatible = "samsung,exynos7-clock-top1";
+ reg = <0x105e0000 0xb000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_topc DOUT_SCLK_BUS0_PLL>,
+ <&clock_topc DOUT_SCLK_BUS1_PLL>,
+ <&clock_topc DOUT_SCLK_CC_PLL>,
+ <&clock_topc DOUT_SCLK_MFC_PLL>;
+ clock-names = "fin_pll",
+ "dout_sclk_bus0_pll",
+ "dout_sclk_bus1_pll",
+ "dout_sclk_cc_pll",
+ "dout_sclk_mfc_pll";
+ };
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 5/8] dt-bindings: clock: samsung: extend Exynos7 bindings with UFS
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
The UFS for Exynos7 SoC clock controller requires additional input
clocks for the FSYS1 clock controller. Update the bindings to reflect
this, at least in theory. In practice, these input clocks are ignored,
so it is rather adjusting of bindings to existing DTS, without affecting
any real users. I understand that is not how it should be done,
though...
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../devicetree/bindings/clock/samsung,exynos7-clock.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
index f3fa6c7ef48b..599baf0b7231 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
@@ -209,14 +209,17 @@ allOf:
then:
properties:
clocks:
- minItems: 4
- maxItems: 4
+ minItems: 7
+ maxItems: 7
clock-names:
items:
- const: fin_pll
- const: dout_aclk_fsys1_200
- const: dout_sclk_mmc0
- const: dout_sclk_mmc1
+ - const: dout_sclk_ufsunipro20
+ - const: dout_sclk_phy_fsys1
+ - const: dout_sclk_phy_fsys1_26m
required:
- clock-names
- clocks
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 5/8] dt-bindings: clock: samsung: extend Exynos7 bindings with UFS
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
The UFS for Exynos7 SoC clock controller requires additional input
clocks for the FSYS1 clock controller. Update the bindings to reflect
this, at least in theory. In practice, these input clocks are ignored,
so it is rather adjusting of bindings to existing DTS, without affecting
any real users. I understand that is not how it should be done,
though...
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../devicetree/bindings/clock/samsung,exynos7-clock.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
index f3fa6c7ef48b..599baf0b7231 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
@@ -209,14 +209,17 @@ allOf:
then:
properties:
clocks:
- minItems: 4
- maxItems: 4
+ minItems: 7
+ maxItems: 7
clock-names:
items:
- const: fin_pll
- const: dout_aclk_fsys1_200
- const: dout_sclk_mmc0
- const: dout_sclk_mmc1
+ - const: dout_sclk_ufsunipro20
+ - const: dout_sclk_phy_fsys1
+ - const: dout_sclk_phy_fsys1_26m
required:
- clock-names
- clocks
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 6/8] dt-bindings: clock: samsung: convert Exynos5260 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos5260 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos5260-clock.txt | 190 ---------
.../clock/samsung,exynos5260-clock.yaml | 382 ++++++++++++++++++
2 files changed, 382 insertions(+), 190 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
deleted file mode 100644
index c79d31f7f66e..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
+++ /dev/null
@@ -1,190 +0,0 @@
-* Samsung Exynos5260 Clock Controller
-
-Exynos5260 has 13 clock controllers which are instantiated
-independently from the device-tree. These clock controllers
-generate and supply clocks to various hardware blocks within
-the SoC.
-
-Each clock is assigned an identifier and client nodes can use
-this identifier to specify the clock which they consume. All
-available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5260-clk.h header and can be used in
-device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It
-is expected that they are defined using standard clock bindings
-with following clock-output-names:
-
- - "fin_pll" - PLL input clock from XXTI
- - "xrtcxti" - input clock from XRTCXTI
- - "ioclk_pcm_extclk" - pcm external operation clock
- - "ioclk_spdif_extclk" - spdif external operation clock
- - "ioclk_i2s_cdclk" - i2s0 codec clock
-
-Phy clocks:
-
-There are several clocks which are generated by specific PHYs.
-These clocks are fed into the clock controller and then routed to
-the hardware blocks. These clocks are defined as fixed clocks in the
-driver with following names:
-
- - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
- - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
- - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
- - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
- - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
- - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
- - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
- - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
- - "phyclk_dptx_phy_clk_div2"
- - "phyclk_mipi_dphy_4l_m_rxclkesc0"
- - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
- - "phyclk_usbhost20_phy_freeclk"
- - "phyclk_usbhost20_phy_clk48mohci"
- - "phyclk_usbdrd30_udrd30_pipe_pclk"
- - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
-
-Required Properties for Clock Controller:
-
- - compatible: should be one of the following.
- 1) "samsung,exynos5260-clock-top"
- 2) "samsung,exynos5260-clock-peri"
- 3) "samsung,exynos5260-clock-egl"
- 4) "samsung,exynos5260-clock-kfc"
- 5) "samsung,exynos5260-clock-g2d"
- 6) "samsung,exynos5260-clock-mif"
- 7) "samsung,exynos5260-clock-mfc"
- 8) "samsung,exynos5260-clock-g3d"
- 9) "samsung,exynos5260-clock-fsys"
- 10) "samsung,exynos5260-clock-aud"
- 11) "samsung,exynos5260-clock-isp"
- 12) "samsung,exynos5260-clock-gscl"
- 13) "samsung,exynos5260-clock-disp"
-
- - reg: physical base address of the controller and the length of
- memory mapped region.
-
- - #clock-cells: should be 1.
-
- - clocks: list of clock identifiers which are fed as the input to
- the given clock controller. Please refer the next section to find
- the input clocks for a given controller.
-
- - clock-names: list of names of clocks which are fed as the input
- to the given clock controller.
-
-Input clocks for top clock controller:
- - fin_pll
- - dout_mem_pll
- - dout_bus_pll
- - dout_media_pll
-
-Input clocks for peri clock controller:
- - fin_pll
- - ioclk_pcm_extclk
- - ioclk_i2s_cdclk
- - ioclk_spdif_extclk
- - phyclk_hdmi_phy_ref_cko
- - dout_aclk_peri_66
- - dout_sclk_peri_uart0
- - dout_sclk_peri_uart1
- - dout_sclk_peri_uart2
- - dout_sclk_peri_spi0_b
- - dout_sclk_peri_spi1_b
- - dout_sclk_peri_spi2_b
- - dout_aclk_peri_aud
- - dout_sclk_peri_spi0_b
-
-Input clocks for egl clock controller:
- - fin_pll
- - dout_bus_pll
-
-Input clocks for kfc clock controller:
- - fin_pll
- - dout_media_pll
-
-Input clocks for g2d clock controller:
- - fin_pll
- - dout_aclk_g2d_333
-
-Input clocks for mif clock controller:
- - fin_pll
-
-Input clocks for mfc clock controller:
- - fin_pll
- - dout_aclk_mfc_333
-
-Input clocks for g3d clock controller:
- - fin_pll
-
-Input clocks for fsys clock controller:
- - fin_pll
- - phyclk_usbhost20_phy_phyclock
- - phyclk_usbhost20_phy_freeclk
- - phyclk_usbhost20_phy_clk48mohci
- - phyclk_usbdrd30_udrd30_pipe_pclk
- - phyclk_usbdrd30_udrd30_phyclock
- - dout_aclk_fsys_200
-
-Input clocks for aud clock controller:
- - fin_pll
- - fout_aud_pll
- - ioclk_i2s_cdclk
- - ioclk_pcm_extclk
-
-Input clocks for isp clock controller:
- - fin_pll
- - dout_aclk_isp1_266
- - dout_aclk_isp1_400
- - mout_aclk_isp1_266
-
-Input clocks for gscl clock controller:
- - fin_pll
- - dout_aclk_gscl_400
- - dout_aclk_gscl_333
-
-Input clocks for disp clock controller:
- - fin_pll
- - phyclk_dptx_phy_ch3_txd_clk
- - phyclk_dptx_phy_ch2_txd_clk
- - phyclk_dptx_phy_ch1_txd_clk
- - phyclk_dptx_phy_ch0_txd_clk
- - phyclk_hdmi_phy_tmds_clko
- - phyclk_hdmi_phy_ref_clko
- - phyclk_hdmi_phy_pixel_clko
- - phyclk_hdmi_link_o_tmds_clkhi
- - phyclk_mipi_dphy_4l_m_txbyte_clkhs
- - phyclk_dptx_phy_o_ref_clk_24m
- - phyclk_dptx_phy_clk_div2
- - phyclk_mipi_dphy_4l_m_rxclkesc0
- - phyclk_hdmi_phy_ref_cko
- - ioclk_spdif_extclk
- - dout_aclk_peri_aud
- - dout_aclk_disp_222
- - dout_sclk_disp_pixel
- - dout_aclk_disp_333
-
-Example 1: An example of a clock controller node is listed below.
-
- clock_mfc: clock-controller@11090000 {
- compatible = "samsung,exynos5260-clock-mfc";
- clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
- clock-names = "fin_pll", "dout_aclk_mfc_333";
- reg = <0x11090000 0x10000>;
- #clock-cells = <1>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the
- peri clock controller. Refer to the standard clock bindings for
- information about 'clocks' and 'clock-names' property.
-
- serial@12c00000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 146 0>;
- clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- };
-
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
new file mode 100644
index 000000000000..a3fac5c6809d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
@@ -0,0 +1,382 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5260 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "fin_pll" - PLL input clock from XXTI
+ - "xrtcxti" - input clock from XRTCXTI
+ - "ioclk_pcm_extclk" - pcm external operation clock
+ - "ioclk_spdif_extclk" - spdif external operation clock
+ - "ioclk_i2s_cdclk" - i2s0 codec clock
+
+ Phy clocks::
+ There are several clocks which are generated by specific PHYs. These clocks
+ are fed into the clock controller and then routed to the hardware blocks.
+ These clocks are defined as fixed clocks in the driver with following names::
+ - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
+ - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
+ - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
+ - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
+ - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
+ - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
+ - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
+ - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
+ - "phyclk_dptx_phy_clk_div2"
+ - "phyclk_mipi_dphy_4l_m_rxclkesc0"
+ - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
+ - "phyclk_usbhost20_phy_freeclk"
+ - "phyclk_usbhost20_phy_clk48mohci"
+ - "phyclk_usbdrd30_udrd30_pipe_pclk"
+ - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos5260-clk.h header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos5260-clock-top
+ - samsung,exynos5260-clock-peri
+ - samsung,exynos5260-clock-egl
+ - samsung,exynos5260-clock-kfc
+ - samsung,exynos5260-clock-g2d
+ - samsung,exynos5260-clock-mif
+ - samsung,exynos5260-clock-mfc
+ - samsung,exynos5260-clock-g3d
+ - samsung,exynos5260-clock-fsys
+ - samsung,exynos5260-clock-aud
+ - samsung,exynos5260-clock-isp
+ - samsung,exynos5260-clock-gscl
+ - samsung,exynos5260-clock-disp
+
+ clocks:
+ minItems: 1
+ maxItems: 19
+
+ clock-names:
+ minItems: 1
+ maxItems: 19
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-top
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_mem_pll
+ - const: dout_bus_pll
+ - const: dout_media_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-peri
+ then:
+ properties:
+ clocks:
+ minItems: 13
+ maxItems: 13
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: ioclk_pcm_extclk
+ - const: ioclk_i2s_cdclk
+ - const: ioclk_spdif_extclk
+ - const: phyclk_hdmi_phy_ref_cko
+ - const: dout_aclk_peri_66
+ - const: dout_sclk_peri_uart0
+ - const: dout_sclk_peri_uart1
+ - const: dout_sclk_peri_uart2
+ - const: dout_sclk_peri_spi0_b
+ - const: dout_sclk_peri_spi1_b
+ - const: dout_sclk_peri_spi2_b
+ - const: dout_aclk_peri_aud
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-egl
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_bus_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-kfc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_media_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-g2d
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_g2d_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-mif
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: fin_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-mfc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_mfc_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-g3d
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: fin_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-fsys
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: phyclk_usbhost20_phy_phyclock
+ - const: phyclk_usbhost20_phy_freeclk
+ - const: phyclk_usbhost20_phy_clk48mohci
+ - const: phyclk_usbdrd30_udrd30_pipe_pclk
+ - const: phyclk_usbdrd30_udrd30_phyclock
+ - const: dout_aclk_fsys_200
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-aud
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: fout_aud_pll
+ - const: ioclk_i2s_cdclk
+ - const: ioclk_pcm_extclk
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-isp
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_isp1_266
+ - const: dout_aclk_isp1_400
+ - const: mout_aclk_isp1_266
+
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-gscl
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_gscl_400
+ - const: dout_aclk_gscl_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-disp
+ then:
+ properties:
+ clocks:
+ minItems: 19
+ maxItems: 19
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: phyclk_dptx_phy_ch3_txd_clk
+ - const: phyclk_dptx_phy_ch2_txd_clk
+ - const: phyclk_dptx_phy_ch1_txd_clk
+ - const: phyclk_dptx_phy_ch0_txd_clk
+ - const: phyclk_hdmi_phy_tmds_clko
+ - const: phyclk_hdmi_phy_ref_clko
+ - const: phyclk_hdmi_phy_pixel_clko
+ - const: phyclk_hdmi_link_o_tmds_clkhi
+ - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
+ - const: phyclk_dptx_phy_o_ref_clk_24m
+ - const: phyclk_dptx_phy_clk_div2
+ - const: phyclk_mipi_dphy_4l_m_rxclkesc0
+ - const: phyclk_hdmi_phy_ref_cko
+ - const: ioclk_spdif_extclk
+ - const: dout_aclk_peri_aud
+ - const: dout_aclk_disp_222
+ - const: dout_sclk_disp_pixel
+ - const: dout_aclk_disp_333
+ required:
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5260-clk.h>
+
+ fin_pll: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ clock-controller@10010000 {
+ compatible = "samsung,exynos5260-clock-top";
+ reg = <0x10010000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEM_PLL>,
+ <&clock_mif MIF_DOUT_BUS_PLL>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_mem_pll",
+ "dout_bus_pll",
+ "dout_media_pll";
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 6/8] dt-bindings: clock: samsung: convert Exynos5260 to dtschema
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos5260 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos5260-clock.txt | 190 ---------
.../clock/samsung,exynos5260-clock.yaml | 382 ++++++++++++++++++
2 files changed, 382 insertions(+), 190 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt b/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
deleted file mode 100644
index c79d31f7f66e..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5260-clock.txt
+++ /dev/null
@@ -1,190 +0,0 @@
-* Samsung Exynos5260 Clock Controller
-
-Exynos5260 has 13 clock controllers which are instantiated
-independently from the device-tree. These clock controllers
-generate and supply clocks to various hardware blocks within
-the SoC.
-
-Each clock is assigned an identifier and client nodes can use
-this identifier to specify the clock which they consume. All
-available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5260-clk.h header and can be used in
-device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It
-is expected that they are defined using standard clock bindings
-with following clock-output-names:
-
- - "fin_pll" - PLL input clock from XXTI
- - "xrtcxti" - input clock from XRTCXTI
- - "ioclk_pcm_extclk" - pcm external operation clock
- - "ioclk_spdif_extclk" - spdif external operation clock
- - "ioclk_i2s_cdclk" - i2s0 codec clock
-
-Phy clocks:
-
-There are several clocks which are generated by specific PHYs.
-These clocks are fed into the clock controller and then routed to
-the hardware blocks. These clocks are defined as fixed clocks in the
-driver with following names:
-
- - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
- - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
- - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
- - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
- - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
- - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
- - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
- - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
- - "phyclk_dptx_phy_clk_div2"
- - "phyclk_mipi_dphy_4l_m_rxclkesc0"
- - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
- - "phyclk_usbhost20_phy_freeclk"
- - "phyclk_usbhost20_phy_clk48mohci"
- - "phyclk_usbdrd30_udrd30_pipe_pclk"
- - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
-
-Required Properties for Clock Controller:
-
- - compatible: should be one of the following.
- 1) "samsung,exynos5260-clock-top"
- 2) "samsung,exynos5260-clock-peri"
- 3) "samsung,exynos5260-clock-egl"
- 4) "samsung,exynos5260-clock-kfc"
- 5) "samsung,exynos5260-clock-g2d"
- 6) "samsung,exynos5260-clock-mif"
- 7) "samsung,exynos5260-clock-mfc"
- 8) "samsung,exynos5260-clock-g3d"
- 9) "samsung,exynos5260-clock-fsys"
- 10) "samsung,exynos5260-clock-aud"
- 11) "samsung,exynos5260-clock-isp"
- 12) "samsung,exynos5260-clock-gscl"
- 13) "samsung,exynos5260-clock-disp"
-
- - reg: physical base address of the controller and the length of
- memory mapped region.
-
- - #clock-cells: should be 1.
-
- - clocks: list of clock identifiers which are fed as the input to
- the given clock controller. Please refer the next section to find
- the input clocks for a given controller.
-
- - clock-names: list of names of clocks which are fed as the input
- to the given clock controller.
-
-Input clocks for top clock controller:
- - fin_pll
- - dout_mem_pll
- - dout_bus_pll
- - dout_media_pll
-
-Input clocks for peri clock controller:
- - fin_pll
- - ioclk_pcm_extclk
- - ioclk_i2s_cdclk
- - ioclk_spdif_extclk
- - phyclk_hdmi_phy_ref_cko
- - dout_aclk_peri_66
- - dout_sclk_peri_uart0
- - dout_sclk_peri_uart1
- - dout_sclk_peri_uart2
- - dout_sclk_peri_spi0_b
- - dout_sclk_peri_spi1_b
- - dout_sclk_peri_spi2_b
- - dout_aclk_peri_aud
- - dout_sclk_peri_spi0_b
-
-Input clocks for egl clock controller:
- - fin_pll
- - dout_bus_pll
-
-Input clocks for kfc clock controller:
- - fin_pll
- - dout_media_pll
-
-Input clocks for g2d clock controller:
- - fin_pll
- - dout_aclk_g2d_333
-
-Input clocks for mif clock controller:
- - fin_pll
-
-Input clocks for mfc clock controller:
- - fin_pll
- - dout_aclk_mfc_333
-
-Input clocks for g3d clock controller:
- - fin_pll
-
-Input clocks for fsys clock controller:
- - fin_pll
- - phyclk_usbhost20_phy_phyclock
- - phyclk_usbhost20_phy_freeclk
- - phyclk_usbhost20_phy_clk48mohci
- - phyclk_usbdrd30_udrd30_pipe_pclk
- - phyclk_usbdrd30_udrd30_phyclock
- - dout_aclk_fsys_200
-
-Input clocks for aud clock controller:
- - fin_pll
- - fout_aud_pll
- - ioclk_i2s_cdclk
- - ioclk_pcm_extclk
-
-Input clocks for isp clock controller:
- - fin_pll
- - dout_aclk_isp1_266
- - dout_aclk_isp1_400
- - mout_aclk_isp1_266
-
-Input clocks for gscl clock controller:
- - fin_pll
- - dout_aclk_gscl_400
- - dout_aclk_gscl_333
-
-Input clocks for disp clock controller:
- - fin_pll
- - phyclk_dptx_phy_ch3_txd_clk
- - phyclk_dptx_phy_ch2_txd_clk
- - phyclk_dptx_phy_ch1_txd_clk
- - phyclk_dptx_phy_ch0_txd_clk
- - phyclk_hdmi_phy_tmds_clko
- - phyclk_hdmi_phy_ref_clko
- - phyclk_hdmi_phy_pixel_clko
- - phyclk_hdmi_link_o_tmds_clkhi
- - phyclk_mipi_dphy_4l_m_txbyte_clkhs
- - phyclk_dptx_phy_o_ref_clk_24m
- - phyclk_dptx_phy_clk_div2
- - phyclk_mipi_dphy_4l_m_rxclkesc0
- - phyclk_hdmi_phy_ref_cko
- - ioclk_spdif_extclk
- - dout_aclk_peri_aud
- - dout_aclk_disp_222
- - dout_sclk_disp_pixel
- - dout_aclk_disp_333
-
-Example 1: An example of a clock controller node is listed below.
-
- clock_mfc: clock-controller@11090000 {
- compatible = "samsung,exynos5260-clock-mfc";
- clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>;
- clock-names = "fin_pll", "dout_aclk_mfc_333";
- reg = <0x11090000 0x10000>;
- #clock-cells = <1>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the
- peri clock controller. Refer to the standard clock bindings for
- information about 'clocks' and 'clock-names' property.
-
- serial@12c00000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 146 0>;
- clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- };
-
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
new file mode 100644
index 000000000000..a3fac5c6809d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
@@ -0,0 +1,382 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5260 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "fin_pll" - PLL input clock from XXTI
+ - "xrtcxti" - input clock from XRTCXTI
+ - "ioclk_pcm_extclk" - pcm external operation clock
+ - "ioclk_spdif_extclk" - spdif external operation clock
+ - "ioclk_i2s_cdclk" - i2s0 codec clock
+
+ Phy clocks::
+ There are several clocks which are generated by specific PHYs. These clocks
+ are fed into the clock controller and then routed to the hardware blocks.
+ These clocks are defined as fixed clocks in the driver with following names::
+ - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
+ - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
+ - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1
+ - "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0
+ - "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock
+ - "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock
+ - "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link
+ - "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock
+ - "phyclk_dptx_phy_clk_div2"
+ - "phyclk_mipi_dphy_4l_m_rxclkesc0"
+ - "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock
+ - "phyclk_usbhost20_phy_freeclk"
+ - "phyclk_usbhost20_phy_clk48mohci"
+ - "phyclk_usbdrd30_udrd30_pipe_pclk"
+ - "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos5260-clk.h header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos5260-clock-top
+ - samsung,exynos5260-clock-peri
+ - samsung,exynos5260-clock-egl
+ - samsung,exynos5260-clock-kfc
+ - samsung,exynos5260-clock-g2d
+ - samsung,exynos5260-clock-mif
+ - samsung,exynos5260-clock-mfc
+ - samsung,exynos5260-clock-g3d
+ - samsung,exynos5260-clock-fsys
+ - samsung,exynos5260-clock-aud
+ - samsung,exynos5260-clock-isp
+ - samsung,exynos5260-clock-gscl
+ - samsung,exynos5260-clock-disp
+
+ clocks:
+ minItems: 1
+ maxItems: 19
+
+ clock-names:
+ minItems: 1
+ maxItems: 19
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-top
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_mem_pll
+ - const: dout_bus_pll
+ - const: dout_media_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-peri
+ then:
+ properties:
+ clocks:
+ minItems: 13
+ maxItems: 13
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: ioclk_pcm_extclk
+ - const: ioclk_i2s_cdclk
+ - const: ioclk_spdif_extclk
+ - const: phyclk_hdmi_phy_ref_cko
+ - const: dout_aclk_peri_66
+ - const: dout_sclk_peri_uart0
+ - const: dout_sclk_peri_uart1
+ - const: dout_sclk_peri_uart2
+ - const: dout_sclk_peri_spi0_b
+ - const: dout_sclk_peri_spi1_b
+ - const: dout_sclk_peri_spi2_b
+ - const: dout_aclk_peri_aud
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-egl
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_bus_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-kfc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_media_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-g2d
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_g2d_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-mif
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: fin_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-mfc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_mfc_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-g3d
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+ clock-names:
+ items:
+ - const: fin_pll
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-fsys
+ then:
+ properties:
+ clocks:
+ minItems: 7
+ maxItems: 7
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: phyclk_usbhost20_phy_phyclock
+ - const: phyclk_usbhost20_phy_freeclk
+ - const: phyclk_usbhost20_phy_clk48mohci
+ - const: phyclk_usbdrd30_udrd30_pipe_pclk
+ - const: phyclk_usbdrd30_udrd30_phyclock
+ - const: dout_aclk_fsys_200
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-aud
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: fout_aud_pll
+ - const: ioclk_i2s_cdclk
+ - const: ioclk_pcm_extclk
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-isp
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_isp1_266
+ - const: dout_aclk_isp1_400
+ - const: mout_aclk_isp1_266
+
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-gscl
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_aclk_gscl_400
+ - const: dout_aclk_gscl_333
+ required:
+ - clock-names
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5260-clock-disp
+ then:
+ properties:
+ clocks:
+ minItems: 19
+ maxItems: 19
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: phyclk_dptx_phy_ch3_txd_clk
+ - const: phyclk_dptx_phy_ch2_txd_clk
+ - const: phyclk_dptx_phy_ch1_txd_clk
+ - const: phyclk_dptx_phy_ch0_txd_clk
+ - const: phyclk_hdmi_phy_tmds_clko
+ - const: phyclk_hdmi_phy_ref_clko
+ - const: phyclk_hdmi_phy_pixel_clko
+ - const: phyclk_hdmi_link_o_tmds_clkhi
+ - const: phyclk_mipi_dphy_4l_m_txbyte_clkhs
+ - const: phyclk_dptx_phy_o_ref_clk_24m
+ - const: phyclk_dptx_phy_clk_div2
+ - const: phyclk_mipi_dphy_4l_m_rxclkesc0
+ - const: phyclk_hdmi_phy_ref_cko
+ - const: ioclk_spdif_extclk
+ - const: dout_aclk_peri_aud
+ - const: dout_aclk_disp_222
+ - const: dout_sclk_disp_pixel
+ - const: dout_aclk_disp_333
+ required:
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5260-clk.h>
+
+ fin_pll: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ clock-controller@10010000 {
+ compatible = "samsung,exynos5260-clock-top";
+ reg = <0x10010000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_mif MIF_DOUT_MEM_PLL>,
+ <&clock_mif MIF_DOUT_BUS_PLL>,
+ <&clock_mif MIF_DOUT_MEDIA_PLL>;
+ clock-names = "fin_pll",
+ "dout_mem_pll",
+ "dout_bus_pll",
+ "dout_media_pll";
+ };
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 7/8] dt-bindings: clock: samsung: convert Exynos5410 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos5410 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos5410-clock.txt | 50 --------------
.../clock/samsung,exynos5410-clock.yaml | 66 +++++++++++++++++++
MAINTAINERS | 1 -
3 files changed, 66 insertions(+), 51 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
deleted file mode 100644
index 217beb27c30e..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Samsung Exynos5410 Clock Controller
-
-The Exynos5410 clock controller generates and supplies clock to various
-controllers within the Exynos5410 SoC.
-
-Required Properties:
-
-- compatible: should be "samsung,exynos5410-clock"
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-- clocks: should contain an entry specifying the root clock from external
- oscillator supplied through XXTI or XusbXTI pin. This clock should be
- defined using standard clock bindings with "fin_pll" clock-output-name.
- That clock is being passed internally to the 9 PLLs.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5410.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
- fin_pll: xxti {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "fin_pll";
- #clock-cells = <0>;
- };
-
- clock: clock-controller@10010000 {
- compatible = "samsung,exynos5410-clock";
- reg = <0x10010000 0x30000>;
- #clock-cells = <1>;
- clocks = <&fin_pll>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
- serial@12c20000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
new file mode 100644
index 000000000000..032862e9f55b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5410 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "fin_pll" - PLL input clock from XXTI
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos5410.h header.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - samsung,exynos5410-clock
+
+ clocks:
+ description:
+ Should contain an entry specifying the root clock from external
+ oscillator supplied through XXTI or XusbXTI pin. This clock should be
+ defined using standard clock bindings with "fin_pll" clock-output-name.
+ That clock is being passed internally to the 9 PLLs.
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5410.h>
+
+ fin_pll: osc-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ clock-controller@10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ea5655a29c3..0aa6a2728a7c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17036,7 +17036,6 @@ M: Chanwoo Choi <cw00.choi@samsung.com>
L: linux-samsung-soc@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
-F: Documentation/devicetree/bindings/clock/exynos*.txt
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
F: Documentation/devicetree/bindings/clock/samsung,s3c*
F: Documentation/devicetree/bindings/clock/samsung,s5p*
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 7/8] dt-bindings: clock: samsung: convert Exynos5410 to dtschema
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung Exynos5410 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/exynos5410-clock.txt | 50 --------------
.../clock/samsung,exynos5410-clock.yaml | 66 +++++++++++++++++++
MAINTAINERS | 1 -
3 files changed, 66 insertions(+), 51 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
deleted file mode 100644
index 217beb27c30e..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Samsung Exynos5410 Clock Controller
-
-The Exynos5410 clock controller generates and supplies clock to various
-controllers within the Exynos5410 SoC.
-
-Required Properties:
-
-- compatible: should be "samsung,exynos5410-clock"
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-- clocks: should contain an entry specifying the root clock from external
- oscillator supplied through XXTI or XusbXTI pin. This clock should be
- defined using standard clock bindings with "fin_pll" clock-output-name.
- That clock is being passed internally to the 9 PLLs.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5410.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
- fin_pll: xxti {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "fin_pll";
- #clock-cells = <0>;
- };
-
- clock: clock-controller@10010000 {
- compatible = "samsung,exynos5410-clock";
- reg = <0x10010000 0x30000>;
- #clock-cells = <1>;
- clocks = <&fin_pll>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
- serial@12c20000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x12C00000 0x100>;
- interrupts = <0 51 0>;
- clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
- clock-names = "uart", "clk_uart_baud0";
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
new file mode 100644
index 000000000000..032862e9f55b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos5410-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos5410 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "fin_pll" - PLL input clock from XXTI
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos5410.h header.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - samsung,exynos5410-clock
+
+ clocks:
+ description:
+ Should contain an entry specifying the root clock from external
+ oscillator supplied through XXTI or XusbXTI pin. This clock should be
+ defined using standard clock bindings with "fin_pll" clock-output-name.
+ That clock is being passed internally to the 9 PLLs.
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5410.h>
+
+ fin_pll: osc-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ clock-controller@10010000 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ea5655a29c3..0aa6a2728a7c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17036,7 +17036,6 @@ M: Chanwoo Choi <cw00.choi@samsung.com>
L: linux-samsung-soc@vger.kernel.org
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
-F: Documentation/devicetree/bindings/clock/exynos*.txt
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
F: Documentation/devicetree/bindings/clock/samsung,s3c*
F: Documentation/devicetree/bindings/clock/samsung,s5p*
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 8/8] dt-bindings: clock: samsung: convert S5Pv210 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung S5Pv210 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/samsung,s5pv210-clock.txt | 77 ------------------
.../bindings/clock/samsung,s5pv210-clock.yaml | 79 +++++++++++++++++++
MAINTAINERS | 1 -
3 files changed, 79 insertions(+), 78 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
deleted file mode 100644
index a86c83bf9d4e..000000000000
--- a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
+++ /dev/null
@@ -1,77 +0,0 @@
-* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
-
-Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
-controller, which generates and supplies clock to various controllers
-within the SoC.
-
-Required Properties:
-
-- compatible: should be one of following:
- - "samsung,s5pv210-clock" : for clock controller of Samsung
- S5PC110/S5PV210 SoCs,
- - "samsung,s5p6442-clock" : for clock controller of Samsung
- S5P6442 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xxti": external crystal oscillator connected to XXTI and XXTO pins of
-the SoC,
- - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
-pins of the SoC,
-
-A subset of above clocks available on given board shall be specified in
-board device tree, including the system base clock, as selected by XOM[0]
-pin of the SoC. Refer to generic fixed rate clock bindings
-documentation[1] for more information how to specify these clocks.
-
-[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
-
-Example: Clock controller node:
-
- clock: clock-controller@7e00f000 {
- compatible = "samsung,s5pv210-clock";
- reg = <0x7e00f000 0x1000>;
- #clock-cells = <1>;
- };
-
-Example: Required external clocks:
-
- xxti: clock-xxti {
- compatible = "fixed-clock";
- clock-output-names = "xxti";
- clock-frequency = <24000000>;
- #clock-cells = <0>;
- };
-
- xusbxti: clock-xusbxti {
- compatible = "fixed-clock";
- clock-output-names = "xusbxti";
- clock-frequency = <24000000>;
- #clock-cells = <0>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller (refer to the standard clock bindings for information about
- "clocks" and "clock-names" properties):
-
- uart0: serial@e2900000 {
- compatible = "samsung,s5pv210-uart";
- reg = <0xe2900000 0x400>;
- interrupt-parent = <&vic1>;
- interrupts = <10>;
- clock-names = "uart", "clk_uart_baud0",
- "clk_uart_baud1";
- clocks = <&clocks UART0>, <&clocks UART0>,
- <&clocks SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
new file mode 100644
index 000000000000..dcb29a2d1159
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
+ the SoC,
+ - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO
+ pins of the SoC,
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/s5pv210.h header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,s5pv210-clock
+ - samsung,s5p6442-clock
+
+ clocks:
+ items:
+ - description: xxti clock
+ - description: xusbxti clock
+
+ clock-names:
+ items:
+ - const: xxti
+ - const: xusbxti
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/s5pv210.h>
+
+ xxti: clock-0 {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "xxti";
+ #clock-cells = <0>;
+ };
+
+ xusbxti: clock-1 {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "xusbxti";
+ #clock-cells = <0>;
+ };
+
+ clock-controller@e0100000 {
+ compatible = "samsung,s5pv210-clock";
+ reg = <0xe0100000 0x10000>;
+ clock-names = "xxti", "xusbxti";
+ clocks = <&xxti>, <&xusbxti>;
+ #clock-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0aa6a2728a7c..d7db7054455d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17038,7 +17038,6 @@ S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
F: Documentation/devicetree/bindings/clock/samsung,s3c*
-F: Documentation/devicetree/bindings/clock/samsung,s5p*
F: drivers/clk/samsung/
F: include/dt-bindings/clock/exynos*.h
F: include/dt-bindings/clock/s3c*.h
--
2.32.0
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH 8/8] dt-bindings: clock: samsung: convert S5Pv210 to dtschema
@ 2022-01-02 11:53 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-02 11:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Sylwester Nawrocki, Tomasz Figa,
Chanwoo Choi, linux-clk, devicetree, linux-arm-kernel,
linux-samsung-soc, linux-kernel
Convert Samsung S5Pv210 SoC clock controller bindings to DT schema
format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
---
.../bindings/clock/samsung,s5pv210-clock.txt | 77 ------------------
.../bindings/clock/samsung,s5pv210-clock.yaml | 79 +++++++++++++++++++
MAINTAINERS | 1 -
3 files changed, 79 insertions(+), 78 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
deleted file mode 100644
index a86c83bf9d4e..000000000000
--- a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
+++ /dev/null
@@ -1,77 +0,0 @@
-* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
-
-Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
-controller, which generates and supplies clock to various controllers
-within the SoC.
-
-Required Properties:
-
-- compatible: should be one of following:
- - "samsung,s5pv210-clock" : for clock controller of Samsung
- S5PC110/S5PV210 SoCs,
- - "samsung,s5p6442-clock" : for clock controller of Samsung
- S5P6442 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
-
-External clocks:
-
-There are several clocks that are generated outside the SoC. It is expected
-that they are defined using standard clock bindings with following
-clock-output-names:
- - "xxti": external crystal oscillator connected to XXTI and XXTO pins of
-the SoC,
- - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
-pins of the SoC,
-
-A subset of above clocks available on given board shall be specified in
-board device tree, including the system base clock, as selected by XOM[0]
-pin of the SoC. Refer to generic fixed rate clock bindings
-documentation[1] for more information how to specify these clocks.
-
-[1] Documentation/devicetree/bindings/clock/fixed-clock.yaml
-
-Example: Clock controller node:
-
- clock: clock-controller@7e00f000 {
- compatible = "samsung,s5pv210-clock";
- reg = <0x7e00f000 0x1000>;
- #clock-cells = <1>;
- };
-
-Example: Required external clocks:
-
- xxti: clock-xxti {
- compatible = "fixed-clock";
- clock-output-names = "xxti";
- clock-frequency = <24000000>;
- #clock-cells = <0>;
- };
-
- xusbxti: clock-xusbxti {
- compatible = "fixed-clock";
- clock-output-names = "xusbxti";
- clock-frequency = <24000000>;
- #clock-cells = <0>;
- };
-
-Example: UART controller node that consumes the clock generated by the clock
- controller (refer to the standard clock bindings for information about
- "clocks" and "clock-names" properties):
-
- uart0: serial@e2900000 {
- compatible = "samsung,s5pv210-uart";
- reg = <0xe2900000 0x400>;
- interrupt-parent = <&vic1>;
- interrupts = <10>;
- clock-names = "uart", "clk_uart_baud0",
- "clk_uart_baud1";
- clocks = <&clocks UART0>, <&clocks UART0>,
- <&clocks SCLK_UART0>;
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
new file mode 100644
index 000000000000..dcb29a2d1159
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,s5pv210-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5P6442/S5PC110/S5PV210 SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
+ - Sylwester Nawrocki <s.nawrocki@samsung.com>
+ - Tomasz Figa <tomasz.figa@gmail.com>
+
+description: |
+ Expected external clocks, defined in DTS as fixed-rate clocks with a matching
+ name::
+ - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
+ the SoC,
+ - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO
+ pins of the SoC,
+
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/s5pv210.h header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,s5pv210-clock
+ - samsung,s5p6442-clock
+
+ clocks:
+ items:
+ - description: xxti clock
+ - description: xusbxti clock
+
+ clock-names:
+ items:
+ - const: xxti
+ - const: xusbxti
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/s5pv210.h>
+
+ xxti: clock-0 {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "xxti";
+ #clock-cells = <0>;
+ };
+
+ xusbxti: clock-1 {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "xusbxti";
+ #clock-cells = <0>;
+ };
+
+ clock-controller@e0100000 {
+ compatible = "samsung,s5pv210-clock";
+ reg = <0xe0100000 0x10000>;
+ clock-names = "xxti", "xusbxti";
+ clocks = <&xxti>, <&xusbxti>;
+ #clock-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0aa6a2728a7c..d7db7054455d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17038,7 +17038,6 @@ S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
F: Documentation/devicetree/bindings/clock/samsung,s3c*
-F: Documentation/devicetree/bindings/clock/samsung,s5p*
F: drivers/clk/samsung/
F: include/dt-bindings/clock/exynos*.h
F: include/dt-bindings/clock/s3c*.h
--
2.32.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH 3/8] dt-bindings: clock: samsung: convert Exynos5433 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-07 1:49 ` Stephen Boyd
-1 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:51)
> Convert Samsung Exynos5433 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 3/8] dt-bindings: clock: samsung: convert Exynos5433 to dtschema
@ 2022-01-07 1:49 ` Stephen Boyd
0 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:51)
> Convert Samsung Exynos5433 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 4/8] dt-bindings: clock: samsung: convert Exynos7 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-07 1:49 ` Stephen Boyd
-1 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:52)
> Convert Samsung Exynos7 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 4/8] dt-bindings: clock: samsung: convert Exynos7 to dtschema
@ 2022-01-07 1:49 ` Stephen Boyd
0 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:52)
> Convert Samsung Exynos7 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 5/8] dt-bindings: clock: samsung: extend Exynos7 bindings with UFS
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-07 1:49 ` Stephen Boyd
-1 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:53)
> The UFS for Exynos7 SoC clock controller requires additional input
> clocks for the FSYS1 clock controller. Update the bindings to reflect
> this, at least in theory. In practice, these input clocks are ignored,
> so it is rather adjusting of bindings to existing DTS, without affecting
> any real users. I understand that is not how it should be done,
> though...
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 5/8] dt-bindings: clock: samsung: extend Exynos7 bindings with UFS
@ 2022-01-07 1:49 ` Stephen Boyd
0 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:53)
> The UFS for Exynos7 SoC clock controller requires additional input
> clocks for the FSYS1 clock controller. Update the bindings to reflect
> this, at least in theory. In practice, these input clocks are ignored,
> so it is rather adjusting of bindings to existing DTS, without affecting
> any real users. I understand that is not how it should be done,
> though...
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/8] dt-bindings: clock: samsung: convert Exynos5260 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-07 1:49 ` Stephen Boyd
-1 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:54)
> Convert Samsung Exynos5260 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/8] dt-bindings: clock: samsung: convert Exynos5260 to dtschema
@ 2022-01-07 1:49 ` Stephen Boyd
0 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:49 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:54)
> Convert Samsung Exynos5260 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/8] dt-bindings: clock: samsung: convert Exynos5410 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-07 1:50 ` Stephen Boyd
-1 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:50 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:55)
> Convert Samsung Exynos5410 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/8] dt-bindings: clock: samsung: convert Exynos5410 to dtschema
@ 2022-01-07 1:50 ` Stephen Boyd
0 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:50 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:55)
> Convert Samsung Exynos5410 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 8/8] dt-bindings: clock: samsung: convert S5Pv210 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-07 1:50 ` Stephen Boyd
-1 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:50 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:56)
> Convert Samsung S5Pv210 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 8/8] dt-bindings: clock: samsung: convert S5Pv210 to dtschema
@ 2022-01-07 1:50 ` Stephen Boyd
0 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2022-01-07 1:50 UTC (permalink / raw)
To: Chanwoo Choi, Krzysztof Kozlowski, Michael Turquette,
Rob Herring, Sylwester Nawrocki, Tomasz Figa, devicetree,
linux-arm-kernel, linux-clk, linux-kernel, linux-samsung-soc
Quoting Krzysztof Kozlowski (2022-01-02 03:53:56)
> Convert Samsung S5Pv210 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 3/8] dt-bindings: clock: samsung: convert Exynos5433 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-10 21:54 ` Rob Herring
-1 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-clk, devicetree, Sylwester Nawrocki, linux-arm-kernel,
Michael Turquette, linux-samsung-soc, Chanwoo Choi, Rob Herring,
Stephen Boyd, linux-kernel, Tomasz Figa
On Sun, 02 Jan 2022 12:53:51 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5433 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos5433-clock.txt | 507 -----------------
> .../clock/samsung,exynos5433-clock.yaml | 524 ++++++++++++++++++
> 2 files changed, 524 insertions(+), 507 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 3/8] dt-bindings: clock: samsung: convert Exynos5433 to dtschema
@ 2022-01-10 21:54 ` Rob Herring
0 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-clk, devicetree, Sylwester Nawrocki, linux-arm-kernel,
Michael Turquette, linux-samsung-soc, Chanwoo Choi, Rob Herring,
Stephen Boyd, linux-kernel, Tomasz Figa
On Sun, 02 Jan 2022 12:53:51 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5433 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos5433-clock.txt | 507 -----------------
> .../clock/samsung,exynos5433-clock.yaml | 524 ++++++++++++++++++
> 2 files changed, 524 insertions(+), 507 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5433-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 4/8] dt-bindings: clock: samsung: convert Exynos7 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-10 21:54 ` Rob Herring
-1 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Michael Turquette, linux-clk, linux-kernel,
linux-samsung-soc, Chanwoo Choi, Stephen Boyd, devicetree,
Sylwester Nawrocki, Tomasz Figa, linux-arm-kernel
On Sun, 02 Jan 2022 12:53:52 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos7 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos7-clock.txt | 108 -------
> .../bindings/clock/samsung,exynos7-clock.yaml | 269 ++++++++++++++++++
> 2 files changed, 269 insertions(+), 108 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 4/8] dt-bindings: clock: samsung: convert Exynos7 to dtschema
@ 2022-01-10 21:54 ` Rob Herring
0 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Michael Turquette, linux-clk, linux-kernel,
linux-samsung-soc, Chanwoo Choi, Stephen Boyd, devicetree,
Sylwester Nawrocki, Tomasz Figa, linux-arm-kernel
On Sun, 02 Jan 2022 12:53:52 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos7 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos7-clock.txt | 108 -------
> .../bindings/clock/samsung,exynos7-clock.yaml | 269 ++++++++++++++++++
> 2 files changed, 269 insertions(+), 108 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 5/8] dt-bindings: clock: samsung: extend Exynos7 bindings with UFS
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-10 21:54 ` Rob Herring
-1 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sylwester Nawrocki, devicetree, Stephen Boyd, linux-arm-kernel,
Rob Herring, linux-kernel, linux-samsung-soc, Chanwoo Choi,
Tomasz Figa, linux-clk, Michael Turquette
On Sun, 02 Jan 2022 12:53:53 +0100, Krzysztof Kozlowski wrote:
> The UFS for Exynos7 SoC clock controller requires additional input
> clocks for the FSYS1 clock controller. Update the bindings to reflect
> this, at least in theory. In practice, these input clocks are ignored,
> so it is rather adjusting of bindings to existing DTS, without affecting
> any real users. I understand that is not how it should be done,
> though...
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../devicetree/bindings/clock/samsung,exynos7-clock.yaml | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
Applied, thanks!
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 5/8] dt-bindings: clock: samsung: extend Exynos7 bindings with UFS
@ 2022-01-10 21:54 ` Rob Herring
0 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:54 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sylwester Nawrocki, devicetree, Stephen Boyd, linux-arm-kernel,
Rob Herring, linux-kernel, linux-samsung-soc, Chanwoo Choi,
Tomasz Figa, linux-clk, Michael Turquette
On Sun, 02 Jan 2022 12:53:53 +0100, Krzysztof Kozlowski wrote:
> The UFS for Exynos7 SoC clock controller requires additional input
> clocks for the FSYS1 clock controller. Update the bindings to reflect
> this, at least in theory. In practice, these input clocks are ignored,
> so it is rather adjusting of bindings to existing DTS, without affecting
> any real users. I understand that is not how it should be done,
> though...
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../devicetree/bindings/clock/samsung,exynos7-clock.yaml | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/8] dt-bindings: clock: samsung: convert Exynos5260 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-10 21:55 ` Rob Herring
-1 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:55 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Michael Turquette, linux-clk, Sylwester Nawrocki,
linux-arm-kernel, linux-samsung-soc, linux-kernel, Chanwoo Choi,
Tomasz Figa, devicetree, Rob Herring, Stephen Boyd
On Sun, 02 Jan 2022 12:53:54 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5260 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos5260-clock.txt | 190 ---------
> .../clock/samsung,exynos5260-clock.yaml | 382 ++++++++++++++++++
> 2 files changed, 382 insertions(+), 190 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 6/8] dt-bindings: clock: samsung: convert Exynos5260 to dtschema
@ 2022-01-10 21:55 ` Rob Herring
0 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 21:55 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Michael Turquette, linux-clk, Sylwester Nawrocki,
linux-arm-kernel, linux-samsung-soc, linux-kernel, Chanwoo Choi,
Tomasz Figa, devicetree, Rob Herring, Stephen Boyd
On Sun, 02 Jan 2022 12:53:54 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5260 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos5260-clock.txt | 190 ---------
> .../clock/samsung,exynos5260-clock.yaml | 382 ++++++++++++++++++
> 2 files changed, 382 insertions(+), 190 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5260-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/8] dt-bindings: clock: samsung: convert Exynos5410 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-10 22:11 ` Rob Herring
-1 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 22:11 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-arm-kernel, Stephen Boyd, Tomasz Figa, Rob Herring,
Chanwoo Choi, devicetree, linux-samsung-soc, linux-clk,
Sylwester Nawrocki, Michael Turquette, linux-kernel
On Sun, 02 Jan 2022 12:53:55 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5410 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos5410-clock.txt | 50 --------------
> .../clock/samsung,exynos5410-clock.yaml | 66 +++++++++++++++++++
> MAINTAINERS | 1 -
> 3 files changed, 66 insertions(+), 51 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 7/8] dt-bindings: clock: samsung: convert Exynos5410 to dtschema
@ 2022-01-10 22:11 ` Rob Herring
0 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 22:11 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-arm-kernel, Stephen Boyd, Tomasz Figa, Rob Herring,
Chanwoo Choi, devicetree, linux-samsung-soc, linux-clk,
Sylwester Nawrocki, Michael Turquette, linux-kernel
On Sun, 02 Jan 2022 12:53:55 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5410 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/exynos5410-clock.txt | 50 --------------
> .../clock/samsung,exynos5410-clock.yaml | 66 +++++++++++++++++++
> MAINTAINERS | 1 -
> 3 files changed, 66 insertions(+), 51 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 8/8] dt-bindings: clock: samsung: convert S5Pv210 to dtschema
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-10 22:11 ` Rob Herring
-1 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 22:11 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-kernel, devicetree, linux-samsung-soc, Rob Herring,
linux-clk, Tomasz Figa, Stephen Boyd, Sylwester Nawrocki,
linux-arm-kernel, Michael Turquette, Chanwoo Choi
On Sun, 02 Jan 2022 12:53:56 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung S5Pv210 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/samsung,s5pv210-clock.txt | 77 ------------------
> .../bindings/clock/samsung,s5pv210-clock.yaml | 79 +++++++++++++++++++
> MAINTAINERS | 1 -
> 3 files changed, 79 insertions(+), 78 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
>
Applied, thanks!
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 8/8] dt-bindings: clock: samsung: convert S5Pv210 to dtschema
@ 2022-01-10 22:11 ` Rob Herring
0 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2022-01-10 22:11 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-kernel, devicetree, linux-samsung-soc, Rob Herring,
linux-clk, Tomasz Figa, Stephen Boyd, Sylwester Nawrocki,
linux-arm-kernel, Michael Turquette, Chanwoo Choi
On Sun, 02 Jan 2022 12:53:56 +0100, Krzysztof Kozlowski wrote:
> Convert Samsung S5Pv210 SoC clock controller bindings to DT schema
> format.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
> ---
> .../bindings/clock/samsung,s5pv210-clock.txt | 77 ------------------
> .../bindings/clock/samsung,s5pv210-clock.yaml | 79 +++++++++++++++++++
> MAINTAINERS | 1 -
> 3 files changed, 79 insertions(+), 78 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
>
Applied, thanks!
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: (subset) [PATCH 1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-23 17:09 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-23 17:09 UTC (permalink / raw)
To: Stephen Boyd, Krzysztof Kozlowski, linux-samsung-soc,
Rob Herring, Chanwoo Choi, linux-clk, Sylwester Nawrocki,
linux-arm-kernel, devicetree, Michael Turquette, Tomasz Figa,
linux-kernel
On Sun, 2 Jan 2022 12:53:49 +0100, Krzysztof Kozlowski wrote:
> Exynos7 devicetree bindings require more input clocks for TOP0 and
> PERIC1 clock controllers, than already provided. Existing DTS was not
> matching the bindings, so let's update the DTS, even though the error
> could be in the bindings.
>
>
Applied, thanks!
[1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7
commit: 372d171cd9b472cff7852211195f211150bc27d2
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: (subset) [PATCH 1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7
@ 2022-01-23 17:09 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-23 17:09 UTC (permalink / raw)
To: Stephen Boyd, Krzysztof Kozlowski, linux-samsung-soc,
Rob Herring, Chanwoo Choi, linux-clk, Sylwester Nawrocki,
linux-arm-kernel, devicetree, Michael Turquette, Tomasz Figa,
linux-kernel
On Sun, 2 Jan 2022 12:53:49 +0100, Krzysztof Kozlowski wrote:
> Exynos7 devicetree bindings require more input clocks for TOP0 and
> PERIC1 clock controllers, than already provided. Existing DTS was not
> matching the bindings, so let's update the DTS, even though the error
> could be in the bindings.
>
>
Applied, thanks!
[1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7
commit: 372d171cd9b472cff7852211195f211150bc27d2
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: (subset) [PATCH 2/8] ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
2022-01-02 11:53 ` Krzysztof Kozlowski
@ 2022-01-23 17:10 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-23 17:10 UTC (permalink / raw)
To: Stephen Boyd, Krzysztof Kozlowski, linux-samsung-soc,
Rob Herring, Chanwoo Choi, linux-clk, Sylwester Nawrocki,
linux-arm-kernel, devicetree, Michael Turquette, Tomasz Figa,
linux-kernel
On Sun, 2 Jan 2022 12:53:50 +0100, Krzysztof Kozlowski wrote:
> Exynos5260 bindings require to feed clock controllers with certain clock
> inputs. The IO clocks are expected to be provided by the board. The
> PHY clocks are usually followed by mux which can choose between the PHY
> clock and main 24 MHz oscillator, so skip defining them and just use the
> latter one.
>
>
> [...]
Applied, thanks!
[2/8] ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
commit: 9eb8090f95e2ef8d19ebce6a77e87b26b56fc831
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: (subset) [PATCH 2/8] ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
@ 2022-01-23 17:10 ` Krzysztof Kozlowski
0 siblings, 0 replies; 44+ messages in thread
From: Krzysztof Kozlowski @ 2022-01-23 17:10 UTC (permalink / raw)
To: Stephen Boyd, Krzysztof Kozlowski, linux-samsung-soc,
Rob Herring, Chanwoo Choi, linux-clk, Sylwester Nawrocki,
linux-arm-kernel, devicetree, Michael Turquette, Tomasz Figa,
linux-kernel
On Sun, 2 Jan 2022 12:53:50 +0100, Krzysztof Kozlowski wrote:
> Exynos5260 bindings require to feed clock controllers with certain clock
> inputs. The IO clocks are expected to be provided by the board. The
> PHY clocks are usually followed by mux which can choose between the PHY
> clock and main 24 MHz oscillator, so skip defining them and just use the
> latter one.
>
>
> [...]
Applied, thanks!
[2/8] ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
commit: 9eb8090f95e2ef8d19ebce6a77e87b26b56fc831
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2022-01-23 17:12 UTC | newest]
Thread overview: 44+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-02 11:53 [PATCH 1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7 Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-02 11:53 ` [PATCH 2/8] ARM: dts: exynos: add necessary clock controller inputs in Exynos5260 Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-23 17:10 ` (subset) " Krzysztof Kozlowski
2022-01-23 17:10 ` Krzysztof Kozlowski
2022-01-02 11:53 ` [PATCH 3/8] dt-bindings: clock: samsung: convert Exynos5433 to dtschema Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-07 1:49 ` Stephen Boyd
2022-01-07 1:49 ` Stephen Boyd
2022-01-10 21:54 ` Rob Herring
2022-01-10 21:54 ` Rob Herring
2022-01-02 11:53 ` [PATCH 4/8] dt-bindings: clock: samsung: convert Exynos7 " Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-07 1:49 ` Stephen Boyd
2022-01-07 1:49 ` Stephen Boyd
2022-01-10 21:54 ` Rob Herring
2022-01-10 21:54 ` Rob Herring
2022-01-02 11:53 ` [PATCH 5/8] dt-bindings: clock: samsung: extend Exynos7 bindings with UFS Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-07 1:49 ` Stephen Boyd
2022-01-07 1:49 ` Stephen Boyd
2022-01-10 21:54 ` Rob Herring
2022-01-10 21:54 ` Rob Herring
2022-01-02 11:53 ` [PATCH 6/8] dt-bindings: clock: samsung: convert Exynos5260 to dtschema Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-07 1:49 ` Stephen Boyd
2022-01-07 1:49 ` Stephen Boyd
2022-01-10 21:55 ` Rob Herring
2022-01-10 21:55 ` Rob Herring
2022-01-02 11:53 ` [PATCH 7/8] dt-bindings: clock: samsung: convert Exynos5410 " Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-07 1:50 ` Stephen Boyd
2022-01-07 1:50 ` Stephen Boyd
2022-01-10 22:11 ` Rob Herring
2022-01-10 22:11 ` Rob Herring
2022-01-02 11:53 ` [PATCH 8/8] dt-bindings: clock: samsung: convert S5Pv210 " Krzysztof Kozlowski
2022-01-02 11:53 ` Krzysztof Kozlowski
2022-01-07 1:50 ` Stephen Boyd
2022-01-07 1:50 ` Stephen Boyd
2022-01-10 22:11 ` Rob Herring
2022-01-10 22:11 ` Rob Herring
2022-01-23 17:09 ` (subset) [PATCH 1/8] arm64: dts: exynos: add necessary clock inputs in Exynos7 Krzysztof Kozlowski
2022-01-23 17:09 ` Krzysztof Kozlowski
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.