From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B0A6C433EF for ; Fri, 4 Feb 2022 11:47:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357014AbiBDLrT (ORCPT ); Fri, 4 Feb 2022 06:47:19 -0500 Received: from foss.arm.com ([217.140.110.172]:38484 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230033AbiBDLrS (ORCPT ); Fri, 4 Feb 2022 06:47:18 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5687F1480; Fri, 4 Feb 2022 03:47:18 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 838873F40C; Fri, 4 Feb 2022 03:47:15 -0800 (PST) Date: Fri, 4 Feb 2022 11:47:25 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Jintack Lim , Haibo Xu , Ganapatrao Kulkarni , Chase Conklin , "Russell King (Oracle)" , James Morse , Suzuki K Poulose , karl.heubaum@oracle.com, mihai.carabas@oracle.com, miguel.luis@oracle.com, kernel-team@android.com Subject: Re: [PATCH v6 09/64] KVM: arm64: nv: Support virtual EL2 exceptions Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-10-maz@kernel.org> <87h79f3kxj.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87h79f3kxj.wl-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Marc, On Thu, Feb 03, 2022 at 05:43:36PM +0000, Marc Zyngier wrote: > On Wed, 02 Feb 2022 15:23:20 +0000, > Alexandru Elisei wrote: > > > > Hi, > > > > On Fri, Jan 28, 2022 at 12:18:17PM +0000, Marc Zyngier wrote: > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > > > new file mode 100644 > > > index 000000000000..f52cd4458947 > > > --- /dev/null > > > +++ b/arch/arm64/kvm/emulate-nested.c > > > @@ -0,0 +1,197 @@ > > > > Looks like this line: > > > > // SPDX-License-Identifier: GPL-2.0-only > > > > is missing. > > Indeed. I should check all the new files, as they are a bit... off. > > > > > > +/* > > > + * Copyright (C) 2016 - Linaro and Columbia University > > > + * Author: Jintack Lim > > > + */ > > > + > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > + > > > +#include "hyp/include/hyp/adjust_pc.h" > > > + > > > +#include "trace.h" > > > + > > > +static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) > > > +{ > > > + u64 mode = spsr & PSR_MODE_MASK; > > > + > > > + /* > > > + * Possible causes for an Illegal Exception Return from EL2: > > > + * - trying to return to EL3 > > > + * - trying to return to a 32bit EL > > > + * - trying to return to EL1 with HCR_EL2.TGE set > > > + */ > > > + if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h || > > > + spsr & PSR_MODE32_BIT || > > > > I take it KVM will not allow a L1 hypervisor to run EL1 or EL0 in 32 > > bit mode? > > No, that'd really be a distraction at this stage. I don't expect any > HW supporting NV NV to support AArch32 at EL1, and if someone really > needs EL0 support (the HW support actually exists), they'll have to > revisit this. > > > > > > + (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || > > > + mode == PSR_MODE_EL1h))) { > > > > I think these checks should also be added: > > > > "A return where the value of the saved process state M[4] bit is 0, > > indicating a return to AArch64 state, and one of the following is > > true: > > > > - The M[1] bit is 1. > > - The M[3:0] bits are 0b0001. > > Definitely should add these two, probably in the form of a switch > enumerating all the possible exception levels rather than checking for > discrete bits that are hard to reason about. > > > - The Exception level being returned to is using AArch32 state, as > > programmed by the SCR_EL3.RW or HCR_EL2.RW bits, or as configured > > from reset." > > That's already caught with the SPSR check above. Hmm... I don't think so. The illegal condition, according to the snippet, should be: !(mode & PSR_MODE32_BIT) && !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_RW) Or, perhaps better, KVM could add an HCR_EL2 accessor that treated the HCR_EL2.RW bit as RA0/WI as per the architecture when the EL1 is not capable of AArch32. That would make the above situation impossible. Thanks, Alex > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB955C433EF for ; Fri, 4 Feb 2022 11:47:23 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 4AAA849E22; Fri, 4 Feb 2022 06:47:23 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id w4dPpHmUk9Qw; Fri, 4 Feb 2022 06:47:21 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id D415949E29; Fri, 4 Feb 2022 06:47:21 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 5E73449E22 for ; Fri, 4 Feb 2022 06:47:20 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 80ALQ4OBoHGM for ; Fri, 4 Feb 2022 06:47:19 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 06C9849B26 for ; Fri, 4 Feb 2022 06:47:18 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5687F1480; Fri, 4 Feb 2022 03:47:18 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 838873F40C; Fri, 4 Feb 2022 03:47:15 -0800 (PST) Date: Fri, 4 Feb 2022 11:47:25 +0000 From: Alexandru Elisei To: Marc Zyngier Subject: Re: [PATCH v6 09/64] KVM: arm64: nv: Support virtual EL2 exceptions Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-10-maz@kernel.org> <87h79f3kxj.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87h79f3kxj.wl-maz@kernel.org> Cc: kernel-team@android.com, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Chase Conklin , kvmarm@lists.cs.columbia.edu, mihai.carabas@oracle.com, Ganapatrao Kulkarni , "Russell King \(Oracle\)" , linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, On Thu, Feb 03, 2022 at 05:43:36PM +0000, Marc Zyngier wrote: > On Wed, 02 Feb 2022 15:23:20 +0000, > Alexandru Elisei wrote: > > > > Hi, > > > > On Fri, Jan 28, 2022 at 12:18:17PM +0000, Marc Zyngier wrote: > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > > > new file mode 100644 > > > index 000000000000..f52cd4458947 > > > --- /dev/null > > > +++ b/arch/arm64/kvm/emulate-nested.c > > > @@ -0,0 +1,197 @@ > > > > Looks like this line: > > > > // SPDX-License-Identifier: GPL-2.0-only > > > > is missing. > > Indeed. I should check all the new files, as they are a bit... off. > > > > > > +/* > > > + * Copyright (C) 2016 - Linaro and Columbia University > > > + * Author: Jintack Lim > > > + */ > > > + > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > + > > > +#include "hyp/include/hyp/adjust_pc.h" > > > + > > > +#include "trace.h" > > > + > > > +static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) > > > +{ > > > + u64 mode = spsr & PSR_MODE_MASK; > > > + > > > + /* > > > + * Possible causes for an Illegal Exception Return from EL2: > > > + * - trying to return to EL3 > > > + * - trying to return to a 32bit EL > > > + * - trying to return to EL1 with HCR_EL2.TGE set > > > + */ > > > + if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h || > > > + spsr & PSR_MODE32_BIT || > > > > I take it KVM will not allow a L1 hypervisor to run EL1 or EL0 in 32 > > bit mode? > > No, that'd really be a distraction at this stage. I don't expect any > HW supporting NV NV to support AArch32 at EL1, and if someone really > needs EL0 support (the HW support actually exists), they'll have to > revisit this. > > > > > > + (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || > > > + mode == PSR_MODE_EL1h))) { > > > > I think these checks should also be added: > > > > "A return where the value of the saved process state M[4] bit is 0, > > indicating a return to AArch64 state, and one of the following is > > true: > > > > - The M[1] bit is 1. > > - The M[3:0] bits are 0b0001. > > Definitely should add these two, probably in the form of a switch > enumerating all the possible exception levels rather than checking for > discrete bits that are hard to reason about. > > > - The Exception level being returned to is using AArch32 state, as > > programmed by the SCR_EL3.RW or HCR_EL2.RW bits, or as configured > > from reset." > > That's already caught with the SPSR check above. Hmm... I don't think so. The illegal condition, according to the snippet, should be: !(mode & PSR_MODE32_BIT) && !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_RW) Or, perhaps better, KVM could add an HCR_EL2 accessor that treated the HCR_EL2.RW bit as RA0/WI as per the architecture when the EL1 is not capable of AArch32. That would make the above situation impossible. Thanks, Alex > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9978AC433EF for ; Fri, 4 Feb 2022 11:49:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nNlrqs3Sx+3+VQ2f3X4Fk30s/bl+Cb8MkBbIOrnbNUI=; b=hENpGqflYFwq79 JR2VYahoc0VGDr936olypM2UnjLDqQs6ciuqZ1y73I3G3kReA18v1fnDdbIjwLsn77JHX5Ox37Shn 9rWsrSIkU/Dzy2rmG/pKfgrmmjd040QKznK9vGyt/ekV6sDinKz1npabdepkUIe4eFmfRs8FY4GkE e0uB4ZmEtZAn0nz+ui9d+KkxRWX9fhF9kc+fXqYcGUFFAOet47HJriORD9UShqbgIo2vBWWdvPgW5 sq4cqK882QXR4ndVzuLqHhtX480Rf0PyRmQgKbt2hsWo6JM4EYTBRQYdf312MEEtYp41lfDVK+Kaq J8GptChJnZc5afxi6OIA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nFx3i-0048eh-LB; Fri, 04 Feb 2022 11:47:22 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nFx3f-0048e0-6M for linux-arm-kernel@lists.infradead.org; Fri, 04 Feb 2022 11:47:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5687F1480; Fri, 4 Feb 2022 03:47:18 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 838873F40C; Fri, 4 Feb 2022 03:47:15 -0800 (PST) Date: Fri, 4 Feb 2022 11:47:25 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Jintack Lim , Haibo Xu , Ganapatrao Kulkarni , Chase Conklin , "Russell King (Oracle)" , James Morse , Suzuki K Poulose , karl.heubaum@oracle.com, mihai.carabas@oracle.com, miguel.luis@oracle.com, kernel-team@android.com Subject: Re: [PATCH v6 09/64] KVM: arm64: nv: Support virtual EL2 exceptions Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-10-maz@kernel.org> <87h79f3kxj.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87h79f3kxj.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220204_034719_350128_A1700D8C X-CRM114-Status: GOOD ( 31.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On Thu, Feb 03, 2022 at 05:43:36PM +0000, Marc Zyngier wrote: > On Wed, 02 Feb 2022 15:23:20 +0000, > Alexandru Elisei wrote: > > > > Hi, > > > > On Fri, Jan 28, 2022 at 12:18:17PM +0000, Marc Zyngier wrote: > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > > > new file mode 100644 > > > index 000000000000..f52cd4458947 > > > --- /dev/null > > > +++ b/arch/arm64/kvm/emulate-nested.c > > > @@ -0,0 +1,197 @@ > > > > Looks like this line: > > > > // SPDX-License-Identifier: GPL-2.0-only > > > > is missing. > > Indeed. I should check all the new files, as they are a bit... off. > > > > > > +/* > > > + * Copyright (C) 2016 - Linaro and Columbia University > > > + * Author: Jintack Lim > > > + */ > > > + > > > +#include > > > +#include > > > + > > > +#include > > > +#include > > > + > > > +#include "hyp/include/hyp/adjust_pc.h" > > > + > > > +#include "trace.h" > > > + > > > +static u64 kvm_check_illegal_exception_return(struct kvm_vcpu *vcpu, u64 spsr) > > > +{ > > > + u64 mode = spsr & PSR_MODE_MASK; > > > + > > > + /* > > > + * Possible causes for an Illegal Exception Return from EL2: > > > + * - trying to return to EL3 > > > + * - trying to return to a 32bit EL > > > + * - trying to return to EL1 with HCR_EL2.TGE set > > > + */ > > > + if (mode == PSR_MODE_EL3t || mode == PSR_MODE_EL3h || > > > + spsr & PSR_MODE32_BIT || > > > > I take it KVM will not allow a L1 hypervisor to run EL1 or EL0 in 32 > > bit mode? > > No, that'd really be a distraction at this stage. I don't expect any > HW supporting NV NV to support AArch32 at EL1, and if someone really > needs EL0 support (the HW support actually exists), they'll have to > revisit this. > > > > > > + (vcpu_el2_tge_is_set(vcpu) && (mode == PSR_MODE_EL1t || > > > + mode == PSR_MODE_EL1h))) { > > > > I think these checks should also be added: > > > > "A return where the value of the saved process state M[4] bit is 0, > > indicating a return to AArch64 state, and one of the following is > > true: > > > > - The M[1] bit is 1. > > - The M[3:0] bits are 0b0001. > > Definitely should add these two, probably in the form of a switch > enumerating all the possible exception levels rather than checking for > discrete bits that are hard to reason about. > > > - The Exception level being returned to is using AArch32 state, as > > programmed by the SCR_EL3.RW or HCR_EL2.RW bits, or as configured > > from reset." > > That's already caught with the SPSR check above. Hmm... I don't think so. The illegal condition, according to the snippet, should be: !(mode & PSR_MODE32_BIT) && !(__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_RW) Or, perhaps better, KVM could add an HCR_EL2 accessor that treated the HCR_EL2.RW bit as RA0/WI as per the architecture when the EL1 is not capable of AArch32. That would make the above situation impossible. Thanks, Alex > > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel